Schematic to Layout Design Flow in Cadence Virtuoso

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  • Опубликовано: 13 янв 2016
  • This video will guide you to how to do circuit design in Cadence Virtuoso schematic and making its layout.

Комментарии • 30

  • @xuansonvu8100
    @xuansonvu8100 4 года назад +3

    struggle with learning this at university. thank you, your video is exacly what i need !

    • @xuansonvu8100
      @xuansonvu8100 4 года назад

      wait at 1:01:18 why my tool does not generate layers? there only the pin. my instructor document me to draw myself the layers. its pretty hard :(

  • @MohsenShahghasemi
    @MohsenShahghasemi 6 лет назад

    That was great Suprovab!

  • @vlsiforbeginners
    @vlsiforbeginners 2 года назад

    Check out full playlist link for Digital IC videos using cadence
    ruclips.net/p/PLRQdEiVtIUAd_yPydulrdS9qwpuBreOZE

  • @FERGOTRESKA
    @FERGOTRESKA 5 лет назад

    Can you please give a brief explanation how to calculate W/L for the transistor size on the video?

  • @chaitanyavemulamada1656
    @chaitanyavemulamada1656 7 лет назад

    Hai Suprovab Mandal,
    Can we draw layout for pnp transistor in cadence or else can we automatically generate layout from schematic that containing a pnp transistor

  • @srinijith
    @srinijith 6 лет назад

    good work can u plz provide me detailed description & Keyboard shortcuts it is very difficult to allign etc

  • @aashutoshgarg986
    @aashutoshgarg986 4 года назад

    Can you please tell how to check power consumption when using AC analysis?

  • @anuragshankhdhar2444
    @anuragshankhdhar2444 7 лет назад

    SIR, i wana to draw layout of vlsi on chip interconnect, kindly suggest how to proceed

  • @deepakprasad7330
    @deepakprasad7330 7 лет назад

    In analog circuit, for gate to gate connection polysilicon is avoided as it has high resistance. Kindly suggest then what can be used for gate to gate connection in analog circuit

  • @waseemakram2918
    @waseemakram2918 5 лет назад

    Hi Mandal, I'm using windows-10 64-bit .Is it possible to invoke the cadence tool in my system ?? could you guide me while installing the application if i get any errors.

  • @hablababla822
    @hablababla822 5 лет назад

    Can you give me the download link of the libraries? Actuator I need UMC_18_CMOS library. It will be helpful for me if you give the direct download link of the library.

  • @kassandrablood7852
    @kassandrablood7852 4 года назад

    Hello my friend, do you know how to copy relative?

  • @ravis4025
    @ravis4025 7 лет назад +1

    Great Mandal

    • @SuprovabMandal
      @SuprovabMandal  7 лет назад

      Thank you sooo much Sir...

    • @Gb-se7ei
      @Gb-se7ei 5 лет назад

      @@SuprovabMandal hi I need your help please tell me zener diode parameters in analoglib in cadence tool

  • @gamewarriorworld4532
    @gamewarriorworld4532 6 лет назад

    hi bro i'm vijay final student can you give some link to download the software for practices.i'm waiting for your response.

  • @KaftiBrizola
    @KaftiBrizola 7 лет назад

    How did your transistors appeared in "pairs" after the "Generate All From Source" ??

    • @SuprovabMandal
      @SuprovabMandal  7 лет назад

      Hi KaftiBrizola,
      If you consider the NAND Gate schematic, then you can observe that both the PMOSs are shared a common connection point i.e. VDD and Drain and same for NMOSs also which share the common connection point i.e. one Drain and one Source. As a result when you are using "Generate All From Source", in the layout window the transistors will appear in pair only if they have shared any common point. Rest of the connection point you have to manually connect.
      Hope this will help you. I'll be glad to hear from you if you face any difficulty.

    • @KaftiBrizola
      @KaftiBrizola 7 лет назад +1

      Wow thank you for the quick response did not expect that!
      I've got exactly the same schematic with yours with the exception that I have connected the Body of the first n-MOS with its Source (On your schematic the NM0 transistor), but I don't think that it makes any difference in the layout. When I do the Generate All From Source, there are 4 separate transistors. The two differences I can see is that we have different versions of Virtuoso (I have 6.1.6 and I saw you have 6.1.5) and that I use another Library for the transistor selection(which uses 65nm technology).
      Thank you again for the help!

  • @pouram
    @pouram 8 лет назад

    can you tell me how to find operating frequency of a transistor.

    • @SuprovabMandal
      @SuprovabMandal  8 лет назад

      +tham Operating frequency of a transistor basically depends on your circuit's operating frequency. It can be in Hz or may be in GHz. So my advice will be please refer your circuit's operating principle.

  • @olivierlettr3650
    @olivierlettr3650 6 лет назад

    Hello Sir,
    Thanks for your video,
    How can I download your instructions?

    • @SuprovabMandal
      @SuprovabMandal  6 лет назад

      Olivier Lettr Thanks for your interest Olivier. But currently I don't have the instruction set with me. Sorry for that.
      I will try to get that from my lab. If I can get then definitely I'll share it with you. 😇

  • @kumar2501
    @kumar2501 7 лет назад

    sir .how to get this software please tell us

    • @SuprovabMandal
      @SuprovabMandal  7 лет назад

      Gaurav kumar This software is available from Cadence. It is available in 2 editions, student and industry.
      If you want to have this then you have to buy this software. You can buy this from Cadence official website.

  • @ShahHarsh1999
    @ShahHarsh1999 3 года назад

    How can i get Reg ID ?