SCHEMATIC TO LAYOUT (PART2)| VIRTUOSO | CADENCE | VLSI | ASIC DESIGN | VLSIFaB

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This is the continuation of my previous video(Nor gate design using full custom flow).In this tutorial, I will be explaining how to make layout directly from the schematic using SCL foundry.
If you want to see the continuation of later parts go to the playlist MTech Project.
VLSIfab playlist are given below:
pnr flow
• pnr
career guidance in vlsi field.
• career guidance in VLS...
Timing and constraints (physical design)
• timing and constraints...
M.TECH project IN VLSI
• M.Tech Project (schem...
PHYSICAL DESIGN FLOW IN DIFFERENT TOOLS OF CADENCE AND SYNOPSYS
• Physical design flow i...

[@learn.sth.useful]

Probably this is the best tutorial on drawing a layout for a small circuit. Congratulations.

[@VLSIFaB]

thanks ..

[@VLSIFaB]

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[@nitin325matker]

Thanks a lot sir for making such nice video
people can learn a lot from this

[@AnkitkumarPandit431]

Thanks sir for such informative video.... I learnt a lot

[@VLSIFaB]

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[@919470583947]

Thank you. Very informative tutorial.

[@misbahmanzoor775]

Thank you sir... Highly appreciate your efforts

[@VLSIFaB]

Thanks...please keep on suggesting as you always do..

[@VLSIFaB]

Please share latest video of vlsifab in your circle ruclips.net/video/xrVyGz6Bzu8/видео.html

[@saharfayaz2281]

Thank you. Your videos are really helpful

[@VLSIFaB]

THANKS ..KINDLY KEEP ON SUGGESTING...FOR MORE INFO YOU CAN CHECK MY WEBSITE...vlsifab.com

[@VLSIFaB]

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[@AdityaKumar-vf4lo]

Only digital layout design video will be uploaded here or you guys is going to upload a analog design video also?

[@VLSIFaB]

analog video also there in the playlist..you can check it.

[@VLSIFaB]

Please share latest video of vlsifab in your circle ruclips.net/video/xrVyGz6Bzu8/видео.html

[@mirmohsinarahman2721]

Sir, we got inductor layout from scl but after using it , we are getting this error:
Netlist Error: Could not find netlist procedure:rfdeMomNetlist_NPORTforSpectre_noRef instance "I9" in cell-view "first_trial" "iwadare_buffer_moscap" "schematic"
End netlisting Jun 1 16:06:25 2018
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
...unsuccessful.
Please help me debug it.

[@VLSIFaB]

hi Mohsina
SORRY FOR LATE REPLY ...I WAS OUT OF STATION..I WILL SURELY CHECK AND WILL REPLY TO YOU.

[@VLSIFaB]

send your mail id madam..i will send you a link which may helpful to you.

[@VLSIFaB]

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[@xuansonvu8100]

pls give me the link of part1. i cant find it in the playlist and seach youtube as well

[@VLSIFaB]

this is the part one/
ruclips.net/video/urZf4BJQApg/видео.html

[@VLSIFaB]

@Sơn Vũ Xuân kinly share vlsifab ruclips.net/channel/UC5oX3fnHimLVEOMygSxAjYw
among your university guys.

[@VLSIFaB]

@Sơn Vũ Xuân from where you are!! China??

[@xuansonvu8100]

​@@VLSIFaB no. im from Viet Nam.
im using VMware to run this tool, the tool is provided by my lab at university.
at 2:03 after "generate --> all from source --> ok" my tool does not generate layers? it only gen the pin. my lab instructor document tell me to draw myself the layers. its pretty hard to draw complex logic gate

[@VLSIFaB]

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