Sir, if I didn't detach the body from the transistors, should I use a separate Via to connect the sources of the transistors to VDD, and GND? Also I saw a method where we draw a Nwell patch over the pmos. Why do we have to do that?
Hi, Since MOS has four terminals. Schematic has 4 terminals. Layout should have 4 terminals. Else leads to LVS error. Alternate method used NWell patch because it is designed using individual layers.
@@dr.hariprasadnaikbhattu So does that depend on the PDK we use? Also if I didn't detach the body from the transistors, should I use a separate Via to connect the sources of the transistors to VDD, and GND?
Hello Sir, I tried to run Assura RCX, and got prompted "No Technology directory found". Do I have to run any command prior to running Virtuoso? Thank you very much.
@@dr.hariprasadnaikbhattu sir same problem for me assura module have been downloaded in gpdk45 but it is not invoking in layout terminal but instead calibre is showing to run drc file
@@dr.hariprasadnaikbhattu while connecting one polysilicon to another polysilicon create path option is not correctly joining the both gates I had to use rectangle to connect finally it was connected
Very helpful, thank you so much may Allah open doors of goodness for you InchAllah
Thanks 🙏
Sir, if I didn't detach the body from the transistors, should I use a separate Via to connect the sources of the transistors to VDD, and GND?
Also I saw a method where we draw a Nwell patch over the pmos. Why do we have to do that?
Hi, Since MOS has four terminals. Schematic has 4 terminals. Layout should have 4 terminals. Else leads to LVS error.
Alternate method used NWell patch because it is designed using individual layers.
@@dr.hariprasadnaikbhattu So does that depend on the PDK we use? Also if I didn't detach the body from the transistors, should I use a separate Via to connect the sources of the transistors to VDD, and GND?
Good explanation sir.thank you.
Welcome
Dear sir,
In av Extracted view only resistors are visible capacitors are not visible.!!!!!!!!!!!!
Thank you sir👌👌👌. Is body tap only at one side enough? In what cases do we need to place guard ring around the mosfet?
Body Tap can be aligned to any one side based on convenience. Guard rings aare placed where sensitive circuitry is located near a noisy circuit.
Sir post a video on layout design for the circuits which are having resistors
Hi I try to make it
Hello Sir, I tried to run Assura RCX, and got prompted "No Technology directory found". Do I have to run any command prior to running Virtuoso? Thank you very much.
Hi, no command but check for assura --> technology
Search for assura tech file
@@dr.hariprasadnaikbhattu Thank you, I have figured out how to solve the issue.
@@HungNguyen-mg2bf Great
@@HungNguyen-mg2bf I am having the same issue. Could you please share the solution.
Sir i can't find assura in the option. I have a option called calibre . Is it the assura ?
Hi, assura and calibre are different. Calibre is more precise
sir can you explain how the design is being fit within a certain number of metal tracks
Those are the metal tracks defined for the cmos technology.
Incredible. Thanks
Welcome
This cadence software is installed on window or linux
Cadence runs on Linux.
Thanks for the Video.
Thanks
Thanks
Welcome
i got errors
NIMP.A.1: Nimp area must be >=0.15 um
PIMP.A.1: Pimp area must be >=0.15 um
what does they mean sir
NIMP are implants of NMOS and PIMP for PMOS.
Very helpful 😊
Welcome
Sir, i don't have assura drop down menu, I am using gpdk045 library. How to solve it?
Assura is a technology file
It must be there
@@dr.hariprasadnaikbhattu sir same problem for me assura module have been downloaded in gpdk45 but it is not invoking in layout terminal but instead calibre is showing to run drc file
@@godavarimanibabu5798 did u get any solution bro? or were u able to do DRC using calibre?
@@hemangnagpal7047 did you get the solution?
Hi sir, If possible make a video on tri-state Inverter and D flip flop
Do you mean layout
@@dr.hariprasadnaikbhattu yes sir
@@jashwanthchowdhary1828 It takes lot of time. Because more gates need to be used .
Thank uu sir❤
You are welcome
zindaabd
good job sir had kai kana
Appreciate your support
@@dr.hariprasadnaikbhattu tanks sir g
Polysilicon contact is not working
Hi, I could not get what was that you are asking
@@dr.hariprasadnaikbhattu while connecting one polysilicon to another polysilicon create path option is not correctly joining the both gates I had to use rectangle to connect finally it was connected
sir can you please help me with memristor emulator
Hi, there is a verilog-a model of memrisrtor to use in cadence.
Try it
how to fix 4] MSLOT1. W.1 MSLOT1.L.1: Metall Slot width/length must be >=0.2 um
Hi, I could not get what you are asking for
@@dr.hariprasadnaikbhattu it is an error when i check DRC
🙏🙏
You are welcome
❤️
👍👍
Welcome