Cadence Virtuoso:: Design of NAND Gate Schematic || Part-1.

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  • Опубликовано: 4 янв 2025

Комментарии • 47

  • @laxmik7618
    @laxmik7618 5 месяцев назад +1

    Very good explanation sir, really u nailed it 👏👏

  • @helloworld-m7s
    @helloworld-m7s 2 месяца назад +2

    one of the excellent video which is very useful.Thnk u sir❤❤❤❤❤❤

  • @chayanaik1391
    @chayanaik1391 Год назад +2

    Thank you so much sir for the detailed explanation with color visualization in the output...

  • @maheshshet3914
    @maheshshet3914 Месяц назад +2

    sir i tried but in the end its showing "spectre terminated prematurely due to fatal error." what's the solution

  • @shrutikkapatel
    @shrutikkapatel 9 месяцев назад +1

    Really very educational video. Thank you.

  • @venkat0536
    @venkat0536 2 месяца назад +1

    How to post in linkedin sir after completing this nand tutorial, and what are the major points we are highlighted and it's(analog and digital both we are mentioned..?) on the linkedin platform I'm confused ..?? Could you tell me sir..? Some major highlighting points...!!

    • @dr.hariprasadnaikbhattu
      @dr.hariprasadnaikbhattu  2 месяца назад +1

      Hi, are asking about the video.
      If you have created use the web post. your youtube link to post on linked in

    • @venkat0536
      @venkat0536 2 месяца назад

      @@dr.hariprasadnaikbhattu no sir I'm just posting photos for the results..!! All in linkedin like PDF..,,

  • @dorinmurmu6482
    @dorinmurmu6482 Месяц назад +1

    Sir I am getting distorted output how to solve it

  • @pushparaj3240
    @pushparaj3240 2 года назад +3

    Thank you very much sir, can you upload the video to do simulation of netlist.v file using nclaunch which is generated in synthesis process.

  • @faizangokak3355
    @faizangokak3355 3 года назад +1

    How to make rise time and fall time are equal if the condition given in the LAB, NAND schematic

    • @dr.hariprasadnaikbhattu
      @dr.hariprasadnaikbhattu  2 года назад

      Hi, Are you asking about output

    • @vlsiforrookies
      @vlsiforrookies 2 года назад

      Check out full playlist link for Digital IC videos using cadence
      ruclips.net/p/PLRQdEiVtIUAd_yPydulrdS9qwpuBreOZE

  • @kirubhakaranraman2096
    @kirubhakaranraman2096 2 года назад +1

    hello sir did you can help how to design 3bit alu
    with A*B, A+B, A-B and AxorB operation c1c0

  • @DAEE_SANJEEVINIPoonaykarbk
    @DAEE_SANJEEVINIPoonaykarbk 4 месяца назад +1

    Sir can you u please send me the specifications of this? I needed it for my mini project

    • @dr.hariprasadnaikbhattu
      @dr.hariprasadnaikbhattu  4 месяца назад +1

      Hi, what do you mean by specification. It is just a NAND gate with four transistor with default values.

  • @sangeetamugali4654
    @sangeetamugali4654 Год назад +1

    Sir this simulation is which technology??

    • @dr.hariprasadnaikbhattu
      @dr.hariprasadnaikbhattu  Год назад +1

      Hi, Simulation is done in gpdk 90nm CMOS technology.

    • @sangeetamugali4654
      @sangeetamugali4654 Год назад

      @@dr.hariprasadnaikbhattu sir I tried in 90nm and 45nm but wave form plots I didn't get.

  • @zheniasg4878
    @zheniasg4878 3 месяца назад +1

    How to correctly build a 4-input NAND gate?🤔

    • @dr.hariprasadnaikbhattu
      @dr.hariprasadnaikbhattu  3 месяца назад +2

      Hi, add another two PMOS in parallel and 2 NMOS transistors in series to the existing.

    • @zheniasg4878
      @zheniasg4878 3 месяца назад

      @@dr.hariprasadnaikbhattu Hi, thanks for the reply! Could you tell me one more thing about the 4-input NAND, how to correctly set the width of the transistors or perhaps some other parameters in order to get the following results at the output:
      Outlet capacity

  • @ebtrabt
    @ebtrabt 2 года назад +1

    very good video, thank you sir

  • @kirubhakaranraman2096
    @kirubhakaranraman2096 2 года назад +1

    how to design multiple design

    • @dr.hariprasadnaikbhattu
      @dr.hariprasadnaikbhattu  2 года назад

      Design individual schematic. Create the symbol. Then bring the any number of symbols to the new design.

  • @vlsiforrookies
    @vlsiforrookies 2 года назад +2

    Check out full playlist link for Digital IC videos using cadence
    ruclips.net/p/PLRQdEiVtIUAd_yPydulrdS9qwpuBreOZE

  • @pavitrakotyal
    @pavitrakotyal 2 года назад +1

    very helpfull sir tku

  • @picnicbros
    @picnicbros Год назад +1

    very easy to understand

  • @preethirajan8995
    @preethirajan8995 3 года назад +2

    Thank you sir 😀

  • @goudappapatil6544
    @goudappapatil6544 22 дня назад +1

    graph is like noise signal

    • @dr.hariprasadnaikbhattu
      @dr.hariprasadnaikbhattu  18 дней назад +1

      Hi, check you have provided the Vdc and gnd. Also check the voltages of pulse source where you gave V V twice while declaring the V1 and V2.

  • @shrutikashinde1377
    @shrutikashinde1377 3 месяца назад +1

    Thank you sir🎉