Around the 20+ min I mistakenly said length of the instance cells should be the same a few times. I meant the HEIGHT should be the same: i.e. the HEIGHT of the inverter cell should be same as that of the XOR. I will soon upload a video showing improvements to this XOR layout.
Don't we also need to connect the Bulk(s) of all the PMOS(s) and NMOS(s) to VDD and Gnd by detaching it using the body tied option?. I think you have not mentioned it during this video, or something else is done to take care of it??. not doing so might cause floating errors!. Pls help :)
Hi，I am a new one to use virtuoso.I want to know the NCSU_TechLib is created by youself or where I can download the library.Because I found there is a few library in library-manager after I have install virtuoso. Think you!
Hi Mark , sorry but I'm not sure I understood the question. I did not use NOR gates to implement this XOR gate, the layout was made using the Wikipedia schematic. You certainly could use 4 NOR Gates (16 transistors)to create a XOR if you'd like, but this way is more compact(12 transistors).
Hi, I’m actually running Cadence by connecting to my former school’s Linux server which hosts the software. Alternatively you can use a Linux virtual machine on a Windows PC.
Around the 20+ min I mistakenly said length of the instance cells should be the same a few times. I meant the HEIGHT should be the same: i.e. the HEIGHT of the inverter cell should be same as that of the XOR.
I will soon upload a video showing improvements to this XOR layout.
no problem, we got it.
I am unable to see my Assura button in layout view . Although I do have files for ASSURA41 . Can someone help ?
Don't we also need to connect the Bulk(s) of all the PMOS(s) and NMOS(s) to VDD and Gnd by detaching it using the body tied option?. I think you have not mentioned it during this video, or something else is done to take care of it??. not doing so might cause floating errors!. Pls help :)
Thank you!! Bro~🥲
Hi，I am a new one to use virtuoso.I want to know the NCSU_TechLib is created by youself or where I can download the library.Because I found there is a few library in library-manager after I have install virtuoso. Think you!
What was the delay of your xor gate
Can you do the xnor pls
thank you very much Sir:) helped with my homework
Hi @Zhengyang G. I find your video to be very helpful. Will you be able to make more of the similar videos in the future?
Only if I get more guitar covers to listen to while editing.
You mistakenly reversed the connection of nMos and Pmos
Check out full playlist link for Digital IC videos using cadence
ruclips.net/p/PLRQdEiVtIUAd_yPydulrdS9qwpuBreOZE
did you use windows 10 for virtuoso 10 without vmware?
No, this was on Linux.
so the part of the layout with 4 poly is a NOR?
Hi Mark , sorry but I'm not sure I understood the question. I did not use NOR gates to implement this XOR gate, the layout was made using the Wikipedia schematic. You certainly could use 4 NOR Gates (16 transistors)to create a XOR if you'd like, but this way is more compact(12 transistors).
thank you, this tutorial helped a lot. Will you be making a Full Adder tutorial in the near future?
@@zhengyangg4708
Glad I was able to help! I actually have most of the full adder components videos recorded but I haven't gotten around to edit them yet.
It may be odd but how did you install cadence virtuoso in windows?
Thanks for the tutorial for the gates
Hi, I’m actually running Cadence by connecting to my former school’s Linux server which hosts the software.
Alternatively you can use a Linux virtual machine on a Windows PC.
Why aren't you naming the vdd net as vdd! and the ground net as gnd! ?
Thank you for the suggestion. Yes that would be the more appropriate method.
XOR Gate Output plz
not(a) b + a not(b)
5:40 layout