Layout of Inverter in Cadence Virtuoso,90 nm-Part1

In this lab demo, we show how to draw the layout of a CMOS inverter using Cadence Virtuoso, Technology-90 nm.

[@siddeshbagali13]

Very helpful, Please come up with more examples and explanations with different analog layout concepts.

[@diehand26]

Thank you

[@NAADHAN1]

Thanks a lot John _/\_

[@anuragshankhdhar2444]

SIR, i wana to draw layout of vlsi on chip interconnect, kindly suggest how to proceed

[@BrindhaThanjavur]

I clicked the option in boundary only while starting layout

[@Gb-se7ei]

Sir told me zener diode parameters in analoglib cadence tool

[@BrindhaThanjavur]

Sir that active area boundary automatically disappears sir. What to do?

[@sumitrana2616]

Respected Sir
I am a 4th yr ECE Student. I am familiar with the Layout designing of basic gates in Cadence Virtuoso using 90nm and 180 nm tech nodes with DRC and LVS. I am looking for guidance from an experienced person related to this field.
Thank You

[@sujatasharma6148]

hi... I have some question regarding 90nm cmos process..Can you help me out

[@riyazuddinmohammed3508]

i got errors
NIMP.A.1: Nimp area must be >=0.15 um
PIMP.A.1: Pimp area must be >=0.15 um
what does they mean sir

[@llndmpcsPavani]

The are of the Pimplant and Nimplant must be greater than the or equal to that values
For example, I am going to take the values that you have taken. The height of the cell is 0.7μm and the length of that implant is considered as 0.3μm then the are going to become 0.21μm it means here your error is clear.
These specifications are going to be generated by the Fabracitaion team hence these values are not fixed for the same technology also it will be dependent on the company of fabrication.