TIME CODE SHORTCUTS: 0:00 Introduction & Open Encounter 1:30 Specify Floorplan 2:55 Power Rings 4:25 Place Pins 6:50 Power Tracks 8:00 Place Standard Cells 9:00 Spare Module 11:30 Zoom & look at cells 12:22 Route Design 14:00 Place Capacitors 15:30 Run Verification 16:50 Timing Reports 17:35 Power Reports 18:55 Save 19:30 Command File
Joe, good afternoon! Was charmed by this video and the way you explain basic things step by step. Thank you very much for such a detailed open-free work. I’ve started working as a chip designer in Encounter Digital Implementation v14.2 tool without any CAD topology engineers around. The only way I can study myself and learn how to provide complete Physical Synthesis are so-called Cadence Rapid Adoption Kits and EDI tutorials. But it seems to be really useless in conditions of real, massive and complicated project I'm working on now. So that’s why I’m desperately searching for somebody, who has at least even once opened an EDI. If it is possible, please, may I have your e-mail or skype-contact just to clear some key important moments in floorplanning and P&R processes. Would be very thankful! Anyway, thank you again. P.S. I know about Cadence Support courses, quite expensive one. But my director is in a long business trip, so there is no one who could manage this issue.
Thank you so much for posting this online. I am only starting to learn about encounter and this is an immense help. I hope one day i will be in a position to provide something to benefit so many people.
Hey guys, this might sound random. We are trying to migrate to RHEL 6 but we have a showstopper issue with EDI 11.0 version which is the version that works on RHEL 6. Students use files /FreePDK45/osu_soc/flow/{encounter.tcl, encounter.conf) as input somewhere. This works fine with EDI10.0 and RHEL5 but we have to EDI110 on rhel 6 and things seem to be broken when using those .tcl scripts in /FreePDK45/osu_soc/flow . Anyone know who can assist updating the .tcl scripts in the flow directory?
Hey Joe.. Nice video.. I am new to encounter. I have worked on version 9.1 where the timing libraries are given at design import. But recently my university shifted to soc encounter version 11.1.. I could not find where to import my max and min timing libraries.. It would be really of great help if you help me out with this problem..
sumanth siddhartha Take a look at the viewDefinition.tcl file in the /pnr directory (it is included from encounter.globals). I'm pretty sure the setup I have posted in the link above will work with encounter version 11+
Why do you need to do that? Typically the spare cells stay in the netlist so you can pass LVS. I suppose you can write a perl script to remove them though.
Thanks for the reply and I found the solution for it. I have an other question. How to route the spare cell which I have created? I have placed a spare cell "NAND3XL" along with the standard cells , now how do I re-route including spare cell which is to be replaced with the same NAND3XL standard cell? I am trying to perform Post-mark ECO.
![FendiDa Rappa - Clock Dat ft. Shamar Marco [Official Music Video]](http://i.ytimg.com/vi/3NBU8KHdxYY/mqdefault.jpg)
TIME CODE SHORTCUTS:
0:00 Introduction & Open Encounter
1:30 Specify Floorplan
2:55 Power Rings
4:25 Place Pins
6:50 Power Tracks
8:00 Place Standard Cells
9:00 Spare Module
11:30 Zoom & look at cells
12:22 Route Design
14:00 Place Capacitors
15:30 Run Verification
16:50 Timing Reports
17:35 Power Reports
18:55 Save
19:30 Command File
Hi ... Please can you add more videos
Joe, good afternoon!
Was charmed by this video and the way you explain basic things step by step. Thank you very much for such a detailed open-free work.
I’ve started working as a chip designer in Encounter Digital Implementation v14.2 tool without any CAD topology engineers around. The only way I can study myself and learn how to provide complete Physical Synthesis are so-called Cadence Rapid Adoption Kits and EDI tutorials. But it seems to be really useless in conditions of real, massive and complicated project I'm working on now. So that’s why I’m desperately searching for somebody, who has at least even once opened an EDI.
If it is possible, please, may I have your e-mail or skype-contact just to clear some key important moments in floorplanning and P&R processes. Would be very thankful!
Anyway, thank you again.
P.S.
I know about Cadence Support courses, quite expensive one. But my director is in a long business trip, so there is no one who could manage this issue.
How can I find the script?
Thanks! Will have somone to take a look. I do have files we use for EDI110, may be I can send you those, to check it out.
Appreciate your help!
Really a nice video for beginners I totally applaud your work Joe,, Well is there any extensions on clock distributions ??
Thank you for sharing such a nice video , but it would have been more useful if you would have explained about clock building.
Thank you so much for posting this online. I am only starting to learn about encounter and this is an immense help. I hope one day i will be in a position to provide something to benefit so many people.
Hey guys, this might sound random. We are trying to migrate to RHEL 6 but we have a showstopper issue with EDI 11.0 version which is the version that works on RHEL 6. Students use files /FreePDK45/osu_soc/flow/{encounter.tcl, encounter.conf) as input somewhere. This works fine with EDI10.0 and RHEL5 but we have to EDI110 on rhel 6 and things seem to be broken when using those .tcl scripts in /FreePDK45/osu_soc/flow . Anyone know who can assist updating the .tcl scripts in the flow directory?
How to reduce wire length I'm floor planning after placing standard cells ?
Easy to understand, very practical...
Hey Joe.. Nice video.. I am new to encounter. I have worked on version 9.1 where the timing libraries are given at design import. But recently my university shifted to soc encounter version 11.1.. I could not find where to import my max and min timing libraries.. It would be really of great help if you help me out with this problem..
sumanth siddhartha Take a look at the viewDefinition.tcl file in the /pnr directory (it is included from encounter.globals). I'm pretty sure the setup I have posted in the link above will work with encounter version 11+
hiiiiiiii, how to eliminate all the errors got in verify geometry?
Try the link in the video description, many files have changed for 11.0 to initialize correctly.
Hi Joe, do you know for sure if MMMC(multi-mode multi corner option) present in EDI110 is supported by FreePDK? Kindly let me know. Thank you!
I'm working on innovus and want to place macros..Can u help me..plz
Please sharing innovus for me? i am student from Ukraine
where did you find this and where can i get more?
Can any one tell me how to create spare cell which are not included in the netlist
Why do you need to do that? Typically the spare cells stay in the netlist so you can pass LVS. I suppose you can write a perl script to remove them though.
Thanks for the reply and I found the solution for it. I have an other question. How to route the spare cell which I have created?
I have placed a spare cell "NAND3XL" along with the standard cells , now how do I re-route including spare cell which is to be replaced with the same NAND3XL standard cell?
I am trying to perform Post-mark ECO.
There is probably a smart way to do this. But I have never had to do it. Sorry
just add the spare cell like inserting filler cell.Any details you can refer to my blog site www.52-ic.com
thanks Joe
:)
Thumb up if you like it, lol
Sorry, I don't know
0
Thank you for quick reply.