ASIC DESIGN- LOGIC SYNTHESIS & PHYSICAL DESIGN USING SYNOPSYS DC AND ICC

This video presents the final group project of our ECE 581 ASIC Modelling and Synthesis course, done by myself (Melvin Sen Thomas), Nancy Rachel Mathen and Saurabh Rabade, all students of Portland State University ECE Department. This video walks through the steps from RTL Design to Logic synthesis and physical design using Synopsys Tools including the various steps involved in PD like floorplanning, P and R, CTS etc using Synopsys Design Compiler and Synopsys IC Compiler. Formal Equivalence verification is done using Cadence Conformal Tool.
Do leave you comments below and if you like the video don't forget to give a thumbs up if it helped you in your course!

[@raveenasaldana3633]

thank you so much, Melvin ! really helpful to know.

[@aarifboy]

IC and DC by Synopsys are free to install, also how or from where you got this tcl script file?

[@saisravan344]

Hi sir, thanks for the video. It is very helpfull for beginners. Can you helpme with the script you might have used for generating final cumulative summary in excel.

[@jitendrasarkar7547]

dear groups can u elaborate deeply in to this domain physical design with another slide upload in youtube .i liked it very much.starting from .thanks

[@raviprakashbr157]

What is the name of this design? What is the operating frequency? Please share it. It will be useful .

[@sivaganesh1862]

thanku sir, please upload me how to get common errors in p. d and please upload

[@thrinadhk4992]

I have one doubt which .extension lib are need for floorplan to gds

[@raviprakashbr157]

.db and .fram