I am totally new to vlsi field and this series enabled my basic understanding about how does synthesis is done. Thanks and apperciated your effort and waiting for more :)
Very thorough and informative lecture, presented in very efficient manner. This is the 1st one I have seen, eager to see rest of them. Can't thank you enough, your students are blessed! Keep up the good work :)
Hi Prof, your sharing has made my source of learning to be here always without going anywhere else. Really thankful for that. Here, I have a quick question on the multibit cell. From your experience, where would be the best way to optimize multibit or the implementation should be starting with? Implementation 1. synthesis : if here, which stages ? 2. If it is pnr: which stages? Post-Implementation 1. What would need to be done in the floorplan in order to ensure the placement of multibit done perfectly without any issue in the power railing, congestion, area and timing. I totally appreciate your kind reply here. You are the best !
Thank you for the kind words. This is exactly why I conceived this course! I'm happy to say that several other universities have adopted it, so I hope I'm "getting the word out".
Hi Ambarish. I touch on this shortly at 1:07:35 of the lecture. ECSM and CCS are what are known as "current source models" (ECSM is the Cadence version and CCS is the Synopsys version - they are slightly different, but provide similar accuracy). In very brief, for NLDM, we assumed a constant ramp input and a constant load capacitance. In the current source models, we figure in a changing input and a changing load, so they provide higher accuracy.
Dear Mr. Teman, Thank you very much for sharing these great lectures with us. You are a great teacher and the presentation of the slides is of top quality. I would be glad if you could answer my following question: I have come across an SDF file type which is an output of the synthesis stage. Do you explain this format in any of the lectures, or if not could you briefly explain the purpose and content of this file type?
Hi Oguz, I am not sure I discuss SDF files specifically in any of the lectures (albeit, in my university course, we export them in the flow and use "SDF backannotation" for post-layout simulation). For the format of SDF files, I suggest you look at the spec on IEEExplore (ieeexplore.ieee.org/document/972829) or search on Google if you cannot access it there. However, just to tell you quickly what the purpose it - This is an ASCII format that enables annotation of delays onto gates and nets. In other words, before synthesis, we use a "zero-delay model", i.e., there are no delays at all in our RTL-level design. However, after mapping the design to actual gates, we can look into the .lib file and find the delays and the output transitions. These can be written out into a file that enables a tool, such as a logic simulator, to apply (close to) real delays to the signals. SDF is the primary format used for this type of "backannotation". Hope that clarified your question.
Very nice lecture! If only all profs would have your teaching style.. One question: You said that CCS means "Concurrent Current Source", but I heard it stands for "Composite Current Source". Do you know what's the correct term here?
Hi Dr.Adam Teman sir,I have follwing two questions 1)What is the internal structure of the filler and Decap cells? 2) What happens if we exchange the Filler cells with End Cap cells? Please explain asap..!
Hi Lalith, good questions. 1) The filler cells are (usually) NWELL and P-active/N-active layers to ensure that the design rules are met. They may also include other layers, such as diffusion and or poly dummies to meet density rules and photolithographic constraints. But in general, they just fill in the empty space, while making sure the design meets the manufacturing constraints. 2) End caps are a "different beast". In many processes they are not (or "were not") needed, but due to various manufacturing constraints, newer processes require them. They "end" the standard cell rows according to a certain definition. One reason, for example, is to minimize WPE (Well Proximity Effects), which cause transistors that are closer to the well edges to have different characteristics than those that are farther away. By adding an end cap, the closest functional transistor the edge of the well is far enough away that this phenomenon is reduced. Another example is the various dummy structures (especially poly and fin) that are required for photolithographic reasons. As for the question if you can swap the two - this really depends on the rules of the process/standard cell library. I can tell you that in certain libraries, the end caps were the same as the well taps, but this is really a specific case. The library should describe to you exactly how a row should be ended and you should adhere to this methodology.
Hi ...Why uniquification is important in Synthesis? Why we are doing uniquification in backend , when while writing Rtl , the instantiations will have different names anyhow .
So, I explain this in Lecture 6 at 24:10 (ruclips.net/video/FUCXqpmdAFA/видео.html). We use instantiation to make design easier - reusing lower level blocks in different places. But when we want to optimize the block, we need to have a separate description of each instantiation of the block and not optimize them all the same. For example, if we have an inverter in a block that is instantiated twice and we want to upsize it in one of the blocks, we do not necessarily want to upsize it in the other.
Hi SK, There are several reasons that could cause different synthesis results; however, the primary reason is the random basis of the algorithms that lie underneath the hood. This is covered in the next lecture (Lecture 4 - ruclips.net/video/lTt2LN7nub0/видео.html). When using optimization algorithms that incur some randomness in them, the solutions will be different by definition. This is important, since the optimization problems are generally NP-complete, meaning that it is infeasible to find the absolute optimal solution, but rather to find a "good" solution, which is some sort of local minimum. By randomizing various parameters (such as the initial solution), there is a better chance that different such local minima will be found and the best one can be chosen.
Dear Sir, Thank you for great explanation. I have only LEF/DEF file from OpenAccess. OpenAccess does not provide netlist file (.V file). May I know how can I use it in Innovus for IR drop Simulation? Thank you Amlesh Kumar
Tough question. Different library vendors provide different files to different clients. OpenAccess is generally a pretty detailed delivery with most of the data you will need (depending on the level of detail it is provided with) and I believe that you can extract a lot of the other views from the OA view and/or use OA views instead of other views in Innovus. Specifically, Verilog behavioral files are the most straightforward file and should be provided, since they are needed for Front End simulation (Gate Level Simulation), but Incisive may also be able to get the info from an OA database, if it includes behavioral views. For IR Drop analysis, many other views are needed, such as Power Grid Views (PGVs), but these also may be provided within OA or can be extracted from it. But you need to turn to an EDA expert to help you with this.
If the question is about "hands-on labs" - I currently do not have these provided as public domain. I am working on this with several companies (e.g., Intel and Cadence) to see if we can figure out a way to provide such materials without infringing IP.
Hi , Wonderful videos!! thanks for giving beautiful explanation. I am into memory layout, I have knowledge on synthesis. Can I move to Physical domain? How is the difficulty level if I move to PD team? thanks in Advance!
Hi Chetana, I am not sure I understand your question. In general, physical design is not easy - otherwise everybody would be doing it (and the salaries would be lower). That being said, my course is intended exactly for people like you to get a jump start into this field and be able to work in a PD team. If you study the lectures and understand them, I think you have a good chance of working in PD.
Well, there to be accurate, standard cells are a type of IP. As mentioned, IP means "intellectual property", which has many meanings (especially in the legal world), but in VLSI engineering, it means something that was developed by someone else. This could be an RTL module, a custom block, or even a verification suite. In this context, you're not usually building your own standard cells and then using them during synthesis, so they are an IP (and even if you did develop them yourself, this would have been done independently, so they would be a separate part of the project). That being said, I refer to very common IP libraries, such as standard cells, I/Os, and SRAMs separately, since they are basically a necessity of any design. This is as opposed to other IPs (for example, an ADC), which you may have and you may not, depending on your required functionality, but if you have it, you will usually be getting it from "somewhere else" (i.e., the guy running synthesis isn't usually the guy designing the ADC), and so it is an IP.
The word "leaf" is referring to a tree. A tree starts with a trunk, then has big branches, smaller branches, and finally, at the end, has leaves. So when we say "leaf cells", we mean the last thing in the design hierarchy. In other words, you have a toplevel, some module that instantiates other modules that instantiate other modules. But finally, you get to the end, where nothing else is instantiated - these are the leaves. In the case of logic, the leaves are standard cells. But leaves can also be hard macros, such as memory blocks, for which we don't have an RTL description, but rather a library (i.e., lib, lef, gds, etc.) that represent the physical cell.
Yes, I believe that the IT of Bar-Ilan University has put some access restrictions due to cybersecurity warnings. I will eventually move the lectures to an external server if they do not resolve this soon. Please feel free to contact me directly (e-mail) if you need a certain lecture PDF in the meantime.
Hi sir.. it was great to see your video thanks a ton ..... Request you to make a video on tracks.. channels... routing tracks... metal layers..and how they are stacked .. I'm unable to comprehend.. if possible guide me a source where I can study them from scratch... thanks a lot sir once again..
Hi Santosh. I have a series of lectures on VLSI circuit design, but unfortunately, I have so far only recorded it in Hebrew. The slides are available in English on my website (www.eng.biu.ac.il/temanad/digital-integrated-circuits/), but it is much better to follow the lectures. I hope to record them in English soon (possibly this semester) so stay tuned.
You are an amazing teacher and a great asset to the world of semiconductors. Thank you for these very informative lectures!
Thank you so much for the kind words!
Can't agree more!
I am totally new to vlsi field and this series enabled my basic understanding about how does synthesis is done. Thanks and apperciated your effort and waiting for more :)
Great to hear!
I have been able to crack interviews of multiple MNC because of the superb lecture delivered by you. Thanks for the selfless effort
Wonderful!
That's the point!
Good luck in whatever job you ultimately choose.
Did you watch all the lectures?
Very thorough and informative lecture, presented in very efficient manner. This is the 1st one I have seen, eager to see rest of them. Can't thank you enough, your students are blessed! Keep up the good work :)
Glad you enjoyed it!
Thank you so much Sir, I am trying to get job in industry after 10 years of long gap and your lectures are helping me a lot. Can't say enough Thanks.
Happy to be providing help!
Thank you, Professor, for the very informative lectures. I am finding it very helpful.
Glad you like them!
I love you Professor! This lecture save my life!! Thanks!!
Happy to hear that!
Hi Prof, your sharing has made my source of learning to be here always without going anywhere else. Really thankful for that.
Here, I have a quick question on the multibit cell. From your experience, where would be the best way to optimize multibit or the implementation should be starting with?
Implementation
1. synthesis : if here, which stages ?
2. If it is pnr: which stages?
Post-Implementation
1. What would need to be done in the floorplan in order to ensure the placement of multibit done perfectly without any issue in the power railing, congestion, area and timing.
I totally appreciate your kind reply here. You are the best !
:D
Thankyou very much for your wonderful explanation.
No one is teaching this concepts for fre and you did it.
Thank you this helps a lot for Freshers 🙏
Thank you for the kind words. This is exactly why I conceived this course! I'm happy to say that several other universities have adopted it, so I hope I'm "getting the word out".
@@AdiTeman ❤️ From India
amazing lecture .. really helps me to learn more in this quarantine period
Thanks for the valueble information sir ..
It's my pleasure.
Thanks for the amazing lecture. Hope to see more. Thanks!!!
More to come!
Thank you for your lecture. I have learned a lot. Your lecture explained many of my previous questions.
You are welcome!
Very very brief lecture.....gives deep knowledge ...great words
Thank you.
Great lecture.
What is the difference between NLDM and ECSM in Liberty models?
Hi Ambarish. I touch on this shortly at 1:07:35 of the lecture. ECSM and CCS are what are known as "current source models" (ECSM is the Cadence version and CCS is the Synopsys version - they are slightly different, but provide similar accuracy). In very brief, for NLDM, we assumed a constant ramp input and a constant load capacitance. In the current source models, we figure in a changing input and a changing load, so they provide higher accuracy.
@@AdiTeman Thank you for the prompt reply. You have helped me out a lot. Great job. Keep it up!
Regards,
Ambarish
Dear Mr. Teman,
Thank you very much for sharing these great lectures with us. You are a great teacher and the presentation of the slides is of top quality.
I would be glad if you could answer my following question: I have come across an SDF file type which is an output of the synthesis stage. Do you explain this format in any of the lectures, or if not could you briefly explain the purpose and content of this file type?
Hi Oguz,
I am not sure I discuss SDF files specifically in any of the lectures (albeit, in my university course, we export them in the flow and use "SDF backannotation" for post-layout simulation). For the format of SDF files, I suggest you look at the spec on IEEExplore (ieeexplore.ieee.org/document/972829) or search on Google if you cannot access it there.
However, just to tell you quickly what the purpose it -
This is an ASCII format that enables annotation of delays onto gates and nets. In other words, before synthesis, we use a "zero-delay model", i.e., there are no delays at all in our RTL-level design. However, after mapping the design to actual gates, we can look into the .lib file and find the delays and the output transitions. These can be written out into a file that enables a tool, such as a logic simulator, to apply (close to) real delays to the signals. SDF is the primary format used for this type of "backannotation".
Hope that clarified your question.
@@AdiTeman Thank you very much for your detailed answer Mr. Teman. Much appreciated.
Thank you for the video Mr.Teeman.
You are very welcome
Very nice lecture! If only all profs would have your teaching style..
One question: You said that CCS means "Concurrent Current Source", but I heard it stands for "Composite Current Source". Do you know what's the correct term here?
Thank you for noticing this. Indeed, the correct name is "Composite Current Source". Sorry for the mistake.
so wonderful lecture
Many thanks
Hi Dr.Adam Teman sir,I have follwing two questions
1)What is the internal structure of the filler and Decap cells?
2) What happens if we exchange the Filler cells with End Cap cells?
Please explain asap..!
Hi Lalith, good questions.
1) The filler cells are (usually) NWELL and P-active/N-active layers to ensure that the design rules are met. They may also include other layers, such as diffusion and or poly dummies to meet density rules and photolithographic constraints. But in general, they just fill in the empty space, while making sure the design meets the manufacturing constraints.
2) End caps are a "different beast". In many processes they are not (or "were not") needed, but due to various manufacturing constraints, newer processes require them. They "end" the standard cell rows according to a certain definition. One reason, for example, is to minimize WPE (Well Proximity Effects), which cause transistors that are closer to the well edges to have different characteristics than those that are farther away. By adding an end cap, the closest functional transistor the edge of the well is far enough away that this phenomenon is reduced. Another example is the various dummy structures (especially poly and fin) that are required for photolithographic reasons.
As for the question if you can swap the two - this really depends on the rules of the process/standard cell library. I can tell you that in certain libraries, the end caps were the same as the well taps, but this is really a specific case. The library should describe to you exactly how a row should be ended and you should adhere to this methodology.
@@AdiTeman Okay sir I got clarity now.Thanks for your time and concern.!
Hi ...Why uniquification is important in Synthesis?
Why we are doing uniquification in backend , when while writing Rtl , the instantiations will have different names anyhow .
So, I explain this in Lecture 6 at 24:10 (ruclips.net/video/FUCXqpmdAFA/видео.html). We use instantiation to make design easier - reusing lower level blocks in different places. But when we want to optimize the block, we need to have a separate description of each instantiation of the block and not optimize them all the same. For example, if we have an inverter in a block that is instantiated twice and we want to upsize it in one of the blocks, we do not necessarily want to upsize it in the other.
@@AdiTeman Thanks 🙏
Shalom brother!
Thanks for the video
My pleasure
What's the reason for different results for the same design in two different synthesis execution?
Hi SK,
There are several reasons that could cause different synthesis results; however, the primary reason is the random basis of the algorithms that lie underneath the hood. This is covered in the next lecture (Lecture 4 - ruclips.net/video/lTt2LN7nub0/видео.html).
When using optimization algorithms that incur some randomness in them, the solutions will be different by definition. This is important, since the optimization problems are generally NP-complete, meaning that it is infeasible to find the absolute optimal solution, but rather to find a "good" solution, which is some sort of local minimum. By randomizing various parameters (such as the initial solution), there is a better chance that different such local minima will be found and the best one can be chosen.
Dear Sir,
Thank you for great explanation. I have only LEF/DEF file from OpenAccess. OpenAccess does not provide netlist file (.V file). May I know how can I use it in Innovus for IR drop Simulation?
Thank you
Amlesh Kumar
Tough question. Different library vendors provide different files to different clients. OpenAccess is generally a pretty detailed delivery with most of the data you will need (depending on the level of detail it is provided with) and I believe that you can extract a lot of the other views from the OA view and/or use OA views instead of other views in Innovus. Specifically, Verilog behavioral files are the most straightforward file and should be provided, since they are needed for Front End simulation (Gate Level Simulation), but Incisive may also be able to get the info from an OA database, if it includes behavioral views. For IR Drop analysis, many other views are needed, such as Power Grid Views (PGVs), but these also may be provided within OA or can be extracted from it. But you need to turn to an EDA expert to help you with this.
Do you have lecture about how to manipulate the software tools in this lecture series? Thank you.
If the question is about "hands-on labs" - I currently do not have these provided as public domain.
I am working on this with several companies (e.g., Intel and Cadence) to see if we can figure out a way to provide such materials without infringing IP.
Hi , Wonderful videos!! thanks for giving beautiful explanation. I am into memory layout, I have knowledge on synthesis. Can I move to Physical domain? How is the difficulty level if I move to PD team? thanks in Advance!
Hi Chetana,
I am not sure I understand your question. In general, physical design is not easy - otherwise everybody would be doing it (and the salaries would be lower). That being said, my course is intended exactly for people like you to get a jump start into this field and be able to work in a PD team. If you study the lectures and understand them, I think you have a good chance of working in PD.
δ λ Is it wrong? Should they swap positions?
Indeed, they did!
Good eye. It is so subtle, that I had a hard time understand what you were pointing out :)
8:30 what is the basic difference between IP and standard cell sir?
Well, there to be accurate, standard cells are a type of IP. As mentioned, IP means "intellectual property", which has many meanings (especially in the legal world), but in VLSI engineering, it means something that was developed by someone else. This could be an RTL module, a custom block, or even a verification suite. In this context, you're not usually building your own standard cells and then using them during synthesis, so they are an IP (and even if you did develop them yourself, this would have been done independently, so they would be a separate part of the project).
That being said, I refer to very common IP libraries, such as standard cells, I/Os, and SRAMs separately, since they are basically a necessity of any design. This is as opposed to other IPs (for example, an ADC), which you may have and you may not, depending on your required functionality, but if you have it, you will usually be getting it from "somewhere else" (i.e., the guy running synthesis isn't usually the guy designing the ADC), and so it is an IP.
are leaf cells are nothing but hard coded block in module? whose name is already written in rtl code
The word "leaf" is referring to a tree. A tree starts with a trunk, then has big branches, smaller branches, and finally, at the end, has leaves. So when we say "leaf cells", we mean the last thing in the design hierarchy. In other words, you have a toplevel, some module that instantiates other modules that instantiate other modules. But finally, you get to the end, where nothing else is instantiated - these are the leaves.
In the case of logic, the leaves are standard cells. But leaves can also be hard macros, such as memory blocks, for which we don't have an RTL description, but rather a library (i.e., lib, lef, gds, etc.) that represent the physical cell.
Very excellent lecture! Why so few views
Thanks! Please send it to your colleagues so there will be more views!
Good course, thank you!
By the way, where can I find lecture slides?
The website seems to be expired.
Yes, I believe that the IT of Bar-Ilan University has put some access restrictions due to cybersecurity warnings. I will eventually move the lectures to an external server if they do not resolve this soon.
Please feel free to contact me directly (e-mail) if you need a certain lecture PDF in the meantime.
My faculty website is back online www.eng.biu.ac.il/temanad/teaching/
Thank you Sir...
Most welcome
Thankyou so much
Most welcome 😊
Hi sir.. it was great to see your video thanks a ton ..... Request you to make a video on tracks.. channels... routing tracks... metal layers..and how they are stacked .. I'm unable to comprehend.. if possible guide me a source where I can study them from scratch... thanks a lot sir once again..
Hi Santosh. I have a series of lectures on VLSI circuit design, but unfortunately, I have so far only recorded it in Hebrew. The slides are available in English on my website (www.eng.biu.ac.il/temanad/digital-integrated-circuits/), but it is much better to follow the lectures. I hope to record them in English soon (possibly this semester) so stay tuned.
@@AdiTeman sure sir will be awaiting for your videos.thanks for the reply sir.__/\__
@@AdiTeman hi prof are the recording in english for the above done...awaiting for your videos prof.. thanks in advance
@@Santoshkumar-lw1gf I am recordng them throughout this semester. The first few classes are online and the others are in their way.
is this university lecture?
Yes, it is part of my Digital VLSI (Backend) Design course at Bar Ilan University.
@@AdiTeman very powerful video, thank you Professor