Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Design Compiler (DC) tutorial

Logic Synthesis is performed once the RTL code is simulated and verified. In Logic Synthesis, A RTL code is converted into a gate-level netlist of given standard cell library.
Logic Synthesis Flow using DC (Design Compiler of Synopsys) has been explained in this tutorial.
In this RTL-to-GDSII flow of video series, there is a total of 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow.
1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow
Video link: • RTL to GDSII flow | Ba...
2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files
Video link: • ASIC Flow and EDA tool...
3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo
Video link: • RTL Design & Simulatio...
4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler
Video link: • Logic Synthesis flow |...
5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate level netlist
Video link: • Logic Synthesis of RTL...
6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision
Video link: • Logic Synthesis in Des...
7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial
Video link: • Logic Equivalence Chec...
8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow
Video link: • Physical Design Flow |...
9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial
Video link: • Design Import | Cadenc...
10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo
Video link: • Place and Route in Cad...
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#LogicSynthesis #DesignCompiler #LogicSynthesisFlow

[@AbhishekKumar-hh8xc]

Thanks a lot for this. I am from simulation background. But I was able grasp most of the things you explained in synthesis with your explanation

[@thatdrownedbiscuit]

Sir
The content is top-notch
But maybe can we eliminate the background noise?

[@byambajavr6519]

Excellent tutorial sir. Thank you :)

[@TeamVLSI]

Thank you.

[@manjunathac3281]

Very good explaination sir. Thank you for uploading this

[@TeamVLSI]

Thanks Manjunatha!

[@yprashant66py]

Great explanation!

[@TeamVLSI]

Thank you :)

[@pratibhajha617]

Hello sir can you please explain the reasons why we are writing constraints to tools and explain thru one small project

[@Narennmallya]

Thank you sir.
One doubt
In this case input is design constraints provided by Vendor(say Synopsys) and output obtained is SDC file which is again a design constraint
so how are they different sir, are they different only in terms of attributes or what? and design constraints are read only files like you said, since we are not allowed to change it. and how about sdc?

[@shri1527]

whats the difference between link library and target library?

[@prasadgadipalli7077]

Target library is subset of link library.
Target library contains stdcells for mapping .
Link library is to resolve references or subdesigns or re usable building blocks or macro libraries or memories

[@raghav9182]

Great video again. Sir, can share something, material/video etc. on the 'timing arc' in standard cell library and how to modify them?

[@TeamVLSI]

Sure, will try. Thanks for the request!

[@bishweshwarprataptasa9918]

Thank you for nice explanation.Can you tell me What is Check design in Design Compiler?

[@TeamVLSI]

Thanks Bishweshwar,
You can check the explanation in our blog.
www.teamvlsi.com/2020/08/sanity-checks-before-floorplan-in.html

[@bishweshwarprataptasa9918]

@@TeamVLSI Thanks...

[@avinashmaheriya8737]

Explanation about the concept is really good. But Sound Quality of video is very Poor.

[@TeamVLSI]

Thank you Avinash
Noted your feedback. You will find good audio in upcoming videos.

[@avinashmaheriya8737]

@@TeamVLSI Thank you very much.

[@vijayak5359]

Your videos are really good and good details explanation but Poor audio quality plz.....find it this problem sir o:-)o:-)

[@mahimasoni6145]

content is good but there is too much background noise, because of which not able to understand properly

[@TeamVLSI]

Thanks Mahima.
Will take care on your feedback.

[@jainyjose4841]

Sir can you make a tutorial on SOC design

[@TeamVLSI]

Hi Jainy,
Yes, In RTL to GDS flow video it is already covered, please check the video.

[@jagruthgowda3006]

Hello Rajesh Sir
1.In which stage of synthesis clockgating cells gets added.
2.On which basis tool will add clockgating cells.
3. Does RTL engineer write verilog code to place clock gating cell in perticular region of your design.

[@prasadgadipalli7077]

1. Clock gates are added after elaboration and before opt and mapping.
3. There are two types of clock gates Architectural clock gates which are added by rtl and inferred clock gates which are added in Synthesis

[@Kalyan14145]

Lots of noise is disturbing
But nice content

[@karthickramki4062]

difference between compile and compile_ultra

[@TeamVLSI]

Compile_ultra is more advance than compile, and it provides better QoR. For more specific details, please refer the DC user guide.