ASIC Flow and EDA tools | Various files used in different stages in ASIC Flow | Back End Flow

RTL to GDSII flow in EDA tool's perspective has explained in this video tutorial. In this video we have discussed various EDA Tools used in the industry in a different stage of ASIC flow. We have also discussed which file sets are required what files generated in different stage of ASIC flow.
In this RTL-to-GDSII flow of video series, there is a total of 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow.
1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow
Video link: • RTL to GDSII flow | Ba...
2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files
Video link: • ASIC Flow and EDA tool...
3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo
Video link: • RTL Design & Simulatio...
4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler
Video link: • Logic Synthesis flow |...
5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate level netlist
Video link: • Logic Synthesis of RTL...
6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision
Video link: • Logic Synthesis in Des...
7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial
Video link: • Logic Equivalence Chec...
8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow
Video link: • Physical Design Flow |...
9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial
Video link: • Design Import | Cadenc...
10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo
Video link: • Place and Route in Cad...
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[@chinmayapanda638]

Sir we need to know how to invoke each packages.
can you please make separate video where invoking of all tools required for RTL2GDSii can be explained.
Also sir please make some video for full custom design using only Cadence tools.

[@TeamVLSI]

Almost all tools basic idea has given . In case you have issue, you can mail me.

[@lokeshmacharla9051]

VCS fullform

[@TeamVLSI]

Sorry Lokesh. I don't know, and believe me no one is going to ask you. :)

[@RobertLugg]

@@TeamVLSI I believe "Verilog Compiled Simulator"