DEF File | Design Exchange Format | Various files in Physical Design | Session -3

In this video tutorial .def (or DEF) file has been explained in details. We have used a sample DEF file to elaborate the exact way in which each section inside the def file is expressed. The general syntax of DEF from DEF language reference manual has also been discussed.
In last of the video, the method to write a DEF file in IC Compiler tools has also been elaborated. In a similar way, one can also write DEF in Innovus tool also.
In this series of Video, we will discuss all important files which are being used in the VLSI Design. We will discuss each file in depth about the content of file and use of all of them. A suitable example will be used to explain the files in the details.
This topic is very important for those who are preparing for the interview and want to join the VLSI Industry, especially in Physical design. Or those who want to understand Physical design flow in the details.
In the next session, we will discuss the Synopsys Constraint file (.sdc file).
Please like the video and subscribe to our channel. You can comment if you have any doubts or you can comment to request on which topic you wish to have a video on this channel.
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#DEF #DesignExchangeFormat #teamVLSI

[@user-bj7pr7gz5x]

i am from INDIA... classes are very useful / Thank you SIR

[@sungmeenmyung6084]

Thank you for the video.

[@TeamVLSI]

Thank you :)

[@rasmiranjansahoo4612]

Great video! Very hard to find such detailed discussion on def

[@TeamVLSI]

Thank you RASMI :)

[@thomasjones-yc8lf]

Very helpful. Thanks.

[@TeamVLSI]

Thanks @thomas, for your feeback.
Stay tuned to the cahnnel for more updates.

[@mukeshkumar-hx9tl]

Thank u sir nd team vlsi for giving us such good explanation!

[@TeamVLSI]

Thanks Mukesh.

[@vivekkumar-po7wh]

What is difference between .def and .nlib file?
Could you please elaborate .nlb file.

[@jetli4696]

very detail, but can you tell the different between DEF for synthesis and DEF after PR?

[@vinodkumarck1919]

You have done a great video, thanks

[@TeamVLSI]

Thanks an lot @Vinod.
Keep supporting!!!

[@habibakhatunnesaragi6259]

Thank u sir for giving such a good explanation. Regards

[@TeamVLSI]

Thank you lots :)

[@NavinKumar-nz6tz]

Sir I have a saed14nm pdk which consist a file lib.def. How to convert that file into .lib or .db file for synthesis a design in synopsys design compiler?

[@TeamVLSI]

Hi Navin,
Check the content of your lib.def file if it is readable that does it has timing info? Or you can mail to your synopsys contact person, and they can provide you .db file of a generic pdk.

[@nfak105]

thanks for detailed explanation (y)

[@TeamVLSI]

You welcome Narinder :)

[@vinodshet27]

Appriciable
Thank you sir.

[@TeamVLSI]

Most welcome vinod and thanks for your appreciation. Keep supporting :)

[@satashreeroy1652]

The screenshots of rows, tracks etc are taken from which tool?

[@TeamVLSI]

Real answer is Vi editor. And from where it is generated has given hint at the end of video.

[@nitishraj1512]

specialnet section not explained clearly.

[@TeamVLSI]

Hi Nitish,
Right, Thanks for Feedback. yes it could have been done in more details.
Thanks