RTL to GDSII flow | Introduction of RTL to GDS Flow | Various EDA tools used in RTL to GDS flow

This video explains the various techniques to prevent Latch-up issue in CMOS technology. Guard ring, well tap cell, retrograde doping, epi layer, Silicon on Insulator (SOI) and many more have been explained in details.
Placement of Well tap cells in physical design and how it helps to prevent the latch-up has also been covered in this session.
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Your queries/suggestions are most welcome in the comment section.
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VIDEOS IN THIS SERIES
1. Latchup issue:
• Latch-up in CMOS Tech...
2. Latchup prevention techniques
• Latch-up prevention in...
3. Antenna effect:
• Antenna effect in VLSI...
4. Antenna prevention techniques
• Antenna Effect Prevent...
5. Electromigration issue in ASIC
• Electromigration in VL...
6. IR Drop Issue in VLSI
• IR Drop issue in VLSI ...
7. On-Chip variations
• On-Chip Variation in V...
8. Crosstalk effect in VLSI
• Crosstalk issue in VLS...
9. Crosstalk prevention
• Crosstalk issue and p...
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[@vikas1093]

Wow! Audio quality is greatly improved. Thanks team vlsi

[@TeamVLSI]

Thanks Vikas.

[@uditnohria9027]

Thank you sir. It was a good brief explanation.

[@TeamVLSI]

Thanks a lot Udit.

[@isaackumba2688]

Wonderfull Thank you for sharing with us this beautiful work

[@TeamVLSI]

My pleasure 😊

[@user-yf9hm5rr2f]

Thanks for your video! It's clear and easily to understand!
I've a little quesion is what's the full name of GDS?
Thanks!!!!

[@TeamVLSI]

GDS is acronyms of Graphic Data Stream. Which contains geometry of all the layers used in layout design.

[@kklin7163]

Good video to understand the RTL to GDS flow. I have one question, I am looking for an advance design standard cell GDS layout for doing electrical simulation. is there any accessible resource? or the only way is doing all this flow?

[@TeamVLSI]

Sorry, I did not get your query. Can you elaborate me what you want?

[@dufferinseng7188]

Thanks for making this ASIC flow introduction video. You can also list physical verification tool. I am not familiar with this stage, are DRC/LVS/ERC using bundled different tools, like Calibre for LVS, DRC using other? not like logic synthesis or PNR, correct me.

[@TeamVLSI]

Yes dear,
Calibre of Mentor graphics is the very popular tool for PV. Other tools are IC Validator (ICV) of Synopsys. Cadence has also tool but very less used for PV.

[@dufferinseng7188]

@@TeamVLSI thanks

[@sarathc1456]

Sir can u explain all numerical problems in setup , hold,CTS,sta etc

[@TeamVLSI]

Yes, I will cover some numericals in STA concepts series.

[@mandavaraviteja]

RTL full form

[@TeamVLSI]

Hi Mandava,
RTL is short form of Register Transfer Level

[@mandavaraviteja]

@@TeamVLSI thank you