LEF file | Technology file | Description of various files used in VLSI Design | session -2

Поделиться
HTML-код
  • Опубликовано: 24 авг 2024

Комментарии • 46

  • @radhikasingh4065
    @radhikasingh4065 4 года назад +2

    Very useful sir your shared information, Thanks for sharing your Knowledge with us

    • @TeamVLSI
      @TeamVLSI  4 года назад

      Thanks @Radhika!
      Keep supporting...

  • @chunhuadeng8770
    @chunhuadeng8770 3 года назад +1

    Very good video, very helpful. Thanks

    • @TeamVLSI
      @TeamVLSI  3 года назад +1

      You're welcome!

  • @bhargavisudina4848
    @bhargavisudina4848 Год назад +1

    Hii Uthkarsh dse topics are soo useful for freshers.

    • @TeamVLSI
      @TeamVLSI  Год назад

      Hi @bhargavi,
      Thanks for you recommendation!

  • @anujparekh752
    @anujparekh752 7 месяцев назад +1

    What is difference between .lef and .tf? how they exactly have some difference?

  • @jetli4696
    @jetli4696 3 года назад +1

    thank you from China

    • @TeamVLSI
      @TeamVLSI  3 года назад

      You are most welcome Jet li. Keep learning keep supporting.

  • @saint2091
    @saint2091 3 года назад +2

    Can you please explain what is implant layer in LEF file? and where its used?

  • @dilliganeshbabu3301
    @dilliganeshbabu3301 4 года назад +3

    Very useful videos. Can you make a tutorial videos on Static Timing Analysis? It will be very useful.

    • @TeamVLSI
      @TeamVLSI  4 года назад

      Thanks @DILLIGANESH
      Sure I have a plan to explain STA very soon.

  • @saint2091
    @saint2091 3 года назад +2

    Can you also upload a video tutorial on how to generate LEF file in Virtuoso?

  • @akhilmalik666
    @akhilmalik666 5 лет назад +2

    Hi.. resistance value of metals layer will be different for each RC corner .
    And resistance in tech lef has only 1 resistance value

    • @TeamVLSI
      @TeamVLSI  5 лет назад

      Alright Akhil, The mentioned value of resistance in technology LEF or in .tf is the typical resistance value for each metal layers. But yes there is variations in resistance in different RC corners.

  • @mr_official_tech7734
    @mr_official_tech7734 2 года назад +1

    Where can we see the which technology we are using like 5nm chip or 7nm chi etc...??

  • @snkhy5631
    @snkhy5631 3 года назад +1

    thank you sir

  • @anushaeerlapati004
    @anushaeerlapati004 Год назад +1

    hi in .lib file also we have cell names,units and pin details and in .lef file also we have the same so, what is the diff?

  • @gurramsanjeev1301
    @gurramsanjeev1301 4 года назад +1

    nice sir ,small request sir do video on double patterning

    • @TeamVLSI
      @TeamVLSI  4 года назад

      Thanks Gurram. keep supporting. We will do that.

  • @StayInBliss
    @StayInBliss 5 лет назад +1

    what a detailing

    • @TeamVLSI
      @TeamVLSI  5 лет назад

      Question is not clear. please ask along with some reference.

    • @StayInBliss
      @StayInBliss 5 лет назад +2

      @@TeamVLSI it's not a question I am saying very good detailing

    • @TeamVLSI
      @TeamVLSI  5 лет назад

      Ohhh Thanks a lot.

  • @akhilmadankar7578
    @akhilmadankar7578 4 года назад +2

    what is the masterslice and where is it used ? ( point 6th in technology lef)

    • @TeamVLSI
      @TeamVLSI  4 года назад +1

      Hi Akhil,
      Masterslice layer is typically poly layers and only needed if the Macro has pins on Poly layer.
      If masterslice layer is defined , one cut layer must be defined between masterslice layer and first routing layer.

  • @aparnareddy7450
    @aparnareddy7450 2 года назад

    Sir.....can you please make a tutorial on DRT analysis in Cadence...?

  • @csS0nNer
    @csS0nNer Год назад

    Thanx for the video. Which tool do you use to edit LEF files?

  • @shivamshrivastava1794
    @shivamshrivastava1794 2 года назад +1

    Hello Sir,
    what is the unit of Resistance(RPERSQ) is it nenometer or something else?

    • @TeamVLSI
      @TeamVLSI  2 года назад

      Hi Shivam,
      Resistance is always measured in Ohm.

  • @abhinavagarwal4924
    @abhinavagarwal4924 Год назад +1

    which file contains information related to frequency?

    • @TeamVLSI
      @TeamVLSI  Год назад

      Hi Abhinav,
      All the clock constraints for PnR come in form of SDC file from synthesis team.

    • @abhinavagarwal4924
      @abhinavagarwal4924 Год назад

      Thank you

  • @abhavsvelidi8828
    @abhavsvelidi8828 2 года назад +1

    What is via in .tf file?

  • @gauravsharma-dy7gs
    @gauravsharma-dy7gs 4 года назад +1

    Can u upload one video on SPEF file? I have a doubt in that.

    • @TeamVLSI
      @TeamVLSI  4 года назад

      Hi Gaurav,
      Thanks for reminding. I will explain SPEF file soon.

  • @kranthikumar339
    @kranthikumar339 Год назад +1

    How to download this pdf in teligram

    • @TeamVLSI
      @TeamVLSI  Год назад

      Hi Kranthi,
      Sorry those slides are not downloadable. better to make your own note if needed from video.

  • @ravivaradarajan1425
    @ravivaradarajan1425 4 года назад +1

    Can you convert a technology LEF file into a .tf file?

  • @graphic_artist06
    @graphic_artist06 Год назад

    Can you please share me the .lef file that would be helpful for my project

  • @arunpandiyananbarasu1455
    @arunpandiyananbarasu1455 4 года назад +1

    What is meant by foreign in Lef

    • @TeamVLSI
      @TeamVLSI  4 года назад

      Hi Arun,
      As per the LEF reference manual
      FOREIGN foreignCellName [pt [orient]]
      Specifies the foreign (GDSII) structure name to use when placing an instance of the macro. The optional pt coordinate specifies the
      macro origin (lower left corner when the macro is in north orientation) offset from the foreign origin. The FOREIGN statement has a default
      offset value of 0 0, if pt is not specified. The optional orient value specifies the orientation of the foreign cell when the macro is in north orientation. The default orient value is N (North).