SDC file | Synopsys Design Constraints file | various files in VLSI Design | session-4

In this video tutorial, Synopsys Design Constraint file (.sdc file | SDC file ) has been explained. Why SDC file is required, when it needs and how to generate sdc file is explained in the first part of this video. In the later part, important constraints of the SDC file has been explained with the help of exact syntax and example of sdc commands.
We have covered basically all of these important commands in sdc file and explained the meaning of each command. Here is the list of some important constraints which we have discussed here.
1. SDC Version
2. Units
System Interface
3. Set driving cells
4. Set load
Design rule constraints
5. Set maximum fanout
6. Set maximum Transition
Timing constraints
7. Create Clock
8. Create Generated Clock
9. Group Path
10. Clock Uncertainty
11. Clock Latency
12. Input Delay
13. Output Delay
Timing Exception
14. Multicycle Path
15. False Path
In this series of video sessions, we will cover 20 most important files used in ASIC design flow.
For more updates, please like the video and subscribe the channel.
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#sdc #SynopsysDesignConstraint #teamVLSI

[@Ravias]

Very useful video, thanks ... great job...

[@TeamVLSI]

Thanks Ravi.

[@taraldc]

Very nicely explain SDC

[@srinathktrsrm7782]

Hello sir, Your videos are very useful. Please make some video for how to fix the parameters mentioned in the SDC. That is how much should we have delay, transition and other parameters for given clock period.

[@TeamVLSI]

Thanks Srinath,
This video was just about the SDC , Basically what is contains. I will elaborate the said point soon :)

[@sekharvakada]

great job sir .. we all love your videos and explanation very well

[@TeamVLSI]

Thank you Sekhar! Its our pleasure. Keep supporting.

[@pvignesh6253]

Thanks for the session 🙏

[@bennguyen1313]

How do you know which I/Oregister, or register-to-register needs to be constrained, or the values to constrain to? Are there any global settings in the tool (quartus or vivaldi) that can optimize parts of the circuit for maximum stability/performance?

[@TeamVLSI]

Not much idea on this Ben.

[@KingSKnocker]

Hello Sir,
These videos are really helpful, Thank you so much for such awesome videos.
Please make some Videos on prime time the way you did for Innovus

[@TeamVLSI]

Thanks Kings
I will demonstrate PT some time later.

[@santhoshd4591]

How to convert the sgdc file to sdc file in Spyglass

[@ashishranjanprasad4943]

I am getting non ANSI interface port error while compiling a .v file, can you tell me how to. Corrent this error

[@TamPham-xj9gj]

great video. Thanks

[@TeamVLSI]

Thanks Pham

[@nephewniece3312]

What are the area constraints??

[@charyvadla4486]

difference between set_driving_cell and set_input_delay ???

[@TeamVLSI]

Both are different. Kindly find the difference in this article.
www.teamvlsi.com/2020/05/sdc-synopsys-design-constraint-file-in.html

[@tuongluongthanh2030]

thank you

[@hannyroy8479]

Sir plz expalin how to define multiple clock in sdc file

[@TeamVLSI]

Sorry for too late response, But I have no idea about this.