LIB file | DB file | Verilog file | Description of various files used in VLSI Design | session-1

In this video tutorial .v file, .vhd file , .lib file, .db file has been explained in details. We have discussed what these files contain and where these files are being used in VLSI design.
In this series of Video, we will discuss all the files which are being used in the VLSI Design. We will discuss each files in depth about the content of file and use of all of them. A suitable example will be used to explain the files in the details.
This topic is very important for those who are preparing for the interview and want to join the VLSI Industry, especially in Physical design. Or those who want to understand Physical design flow in the details.
In the next session, we will discuss .lef file, and .tf file.
Here is the link for a video which demonstrates the .lib to .db file conversion
• Library files format c...
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#LIB #DB #Verilog #teamVLSI

[@rammutyala3419]

i hv not seen this much of slow and v clear explanation tq soooooo much sir .

[@TeamVLSI]

Keep watching

[@sakthiarun2440]

Good Work VLSI Team..!! Appreciating for your effective work..!!

[@TeamVLSI]

Thanks @Arun

[@sylviasiew0515]

Thank you so much for putting so much effort in creating this video for us to understand the files.

[@TeamVLSI]

Hi Sylvia,
You're very welcome, We try our best to make the video simple and understandable to all.

[@AbhishekKumar-td4oq]

sir your effort is appreciable.From your sharing accurate information which help in many ways as interview aspect and knowlegde.So keep it up sir.

[@TeamVLSI]

Thanks Abhishek
Its my pleasure that you like the content and such appreciations work like a fuel for me to keep moving. :)

[@rohitharohi494]

Thank u so much for whole vlsi team this channel is very helpful for pd freshers .... i see a lot of videos from ur channel .....Really good content and easy to learn ...............

[@TeamVLSI]

Thanks you so much @Rohitha. Keep motivating us by your comments and support the channel by just liking and sharing the video.

[@kshitij8810]

great content sir.....
thank you very much..

[@TeamVLSI]

Thanks Kshitij!

[@anushatadamari3185]

Very helpful sir.. please keep posting videos🙏🙏

[@TeamVLSI]

Sure 👍

[@akhilmalik666]

Hi.. can you make 1 detailed video of .lib explaining look up table for cell delay, setup/hold time, power.
I mean to say like how all these are function of slew rate,load , can you explain that concept.
It would be really helpful.
Thanks

[@rheeshaalaensabapathy6063]

is there any video related to this

[@Vi-vp3us]

Thank you very much for recording this video in English :)

[@TeamVLSI]

Thank you dear!

[@venkatmadaka123]

can you please do videos on Xilinx vivado 2017.2 for doing synthesis of combinational and sequential circuits. and also discuss which files are needed to do the synthesis

[@palakagarwal7156]

Very informative

[@TeamVLSI]

Thanks Palak!
Glad you liked it. Keep supporting, keep learning.

[@rafaelneves9834]

Very good! Thank you!

[@TeamVLSI]

Hi Rafael,
Thank you too! Stay tune for more such videos.

[@nilrathod9840]

Good explanation. Thank you!

[@nitiningle1991]

Appreciate your efforts. Keep doing it.

[@TeamVLSI]

Thanks Nitin :)

[@sridharchandrasekar7787]

Nice lecture bro...i have one doubt..how to design memory by using pdk

[@matoorirajesh1396]

thank you sir

[@TeamVLSI]

Most welcome dear! keep supporting :)

[@chaitannandan4511]

What is rise capacitance and fall capacitance

[@sudheerreddy3432]

Can you explain what information consist in cshrc file and pr summary file in physical verification process

[@TeamVLSI]

Could you please let me know about more of these files, When it generates, by which tools?

[@deoncrasta9595]

How to use liberate tool??

[@ankitsingh8813]

are these helpful for fresher dft engineers as well?

[@TeamVLSI]

Yes @Ankit.

[@praveenlokanadham1803]

Can you please elaborate why CCS is more accurate than nldm

[@TeamVLSI]

Hi Praveen
This article might help you to understand these models in better way .
www.paripath.com/blog/characterization-blog/comparing-nldm-and-ccs-delay-models

[@KavitaSharma-wm7wq]

CCS have more variable around 20 to calculate delay ...and ndlm have only 2 variable that's why...and runtime also more for ccs because of more variable and file size also long for ccs ...

[@rammutyala3419]

@@KavitaSharma-wm7wq could u tell me what that variables atleast some

[@mrshashi4u]

Very informative, What are the units for all those values? Ex area is interms of um2 or nm2?

[@TeamVLSI]

Hi Shashidhar
Thank you.
Unit of area is derived from database unit. Database unit is generally in micron. So unit of area is um^2

[@bganeshp5484]

hello sir. can you please give information about .sdf file as well ?

[@TeamVLSI]

Sure Ganesh, I will do that.

[@narendrapratapsharma2287]

I this lecture is recorded by aghaz khan?

[@TeamVLSI]

No.

[@mr-fahim-khan]

Hindy me bolo bro

[@snkhy5631]

thank you sir

[@TeamVLSI]

Most welcome