Exactly, I have a deep experience in the field and am super impressed by the depth and breadth of the knowledge he drops in each and every video. The part I can't figure out is how he does it so fast. Truly gifted at this.
I recently found out that costa rica has a pretty big semiconductor industry, I find it to be very odd choice for such an industry focused mostly in east asia and the USA. A video on that would be very interesting imo
7:08 DTCO - Design Technology Co-Optimization. That is a really important concept in semiconductor design and manufacturing, and can be applied in a lot of other industries as well.
DTCO is a fancy term for talking to the client, and is a crutch solution. While talking to the client is still necessary, and beneficial, it can and should be reserved for edge cases and critical design and wisdom, not holding their hand through the rote basics. The fabs could have categorized and tagged each rule better as required, optional, and quantifying what the tradeoffs are for the optional ones. Then they could make all this cataloguing searchable and self-explained via a simple web app, where the chip designers can reference, search, filter, sort rules easily by tag, and the quantified tradeoffs can be presented in a straightforward manner. Then DTCO can focus on the questions that really matter, and be a source of feedback, which continually gets incorporated into improving the web app for more rules, deprecating rules, etc.
Love this video and so many of the ones you make. This video has a lot of call backs to older videos you make. If you reference a video, could you also link it in the description? Would make it a lot easier to bounce over to that video for context and then bounce back when done. Keep up the great work!
Xilinx was known for their incredibly tight relationship with TSMC. AMD, having owned their own fabs previously, was already intimate with working directly with the lithography department, so they quickly ascended the same stairs with TSMC. Today AMD owns Xilinx, and it is speculated that their ultimate goal is to beat Apple to the leading edge and become the premier partner of TSMC. If that happens I think both Intel and Nvidia will be in long term trouble...
but apple had tremendous amount of cash on his pocket (yeap real reserve cash from sellin iphone) they can buy all new tsmc node volume like 100% all off it production year long
I speculate that you’re talking out your ass lol. Idk how you think the tiny Xilinx arm of amd is going to displace Apple. Not unless Apple decides to build their own fabs 😂
@@zunriya what it depends on is if Apple stops innovating like they did t with the iPhone 14, they reuse the same old chip as last year, only updating the iPhone Pro. If competitors don't catch up they will likely not push the bleeding edge as hard
This past week I was reading your article on the Perkin-Elmer blog. Very well done! Thanks for making it so approachable for those who might not be in the field. 👍
@@ntabilePerkin Elmer? Perkin Elmer started in optics. Creating telescopes, bomb sights and the optics of spy satellites, by the late '60's they had military contracts to fab semiconductors and by the mid '70's were selling the Micralign projection system. This semiconductor division got sold to SVG and ultimately became ASML Wilton. They were also deep into analytical lab equipment and pioneers of PCR with their genomics division. There was a lot of micro fluidics and chromatography going on, so I guess 'pumps' in a way...
"It's like haggling at a Taiwan night market" brought back wonderful memories of a visit to Kaosiung some time ago. But now I'll have to watch this one again after writing down the acronyms. I want to savor the details and Google search some of the principles. Also want to see how they apply to GPUs and the special chips coming out for AI research. Interesting stuff.... Cheers!
I suspect that AI is in it's early infancy and that in 5 - 10 years this time of AI computing will seem extremely archaic. Will Nvidia be seen as a leader of AI in 10 years or an extinct dinosaur
Your mention of Acronyms, brought me a Chuckle. When I Worked at Intel, and Attended Meetings, I was overwhelmed by the Acronyms. At next Meeting, I was Handed an Intel Acronym Dictionary, LOL.
Great Video. I am very stunned to know the technicalities behind the chip design, Thank you so much for this video. All your videos about TSMC / chip making makes me feel like working on chips :)
I think it’s worth repeating that I have zero idea how any of this stuff works, but that I’m totally captivated by these videos. Very informative, but I have no idea what the information is😅
At 1:58 shoudn't it be the other way around? That the wavelength of the light was smaller than the feature size? I assume that you need wavelengths smaller than the feature size you're etching or am i missing something
Thank you, thank you, thank you! It'd the best overview of the history of the chip design process. I'm wondering if you could compare ASMC and Intel design processes. Such a video would be extremely interesting! I would highly appreciate such a comparison!
as someone in university labs working on 300nm EBL. its insane to think about how these people are making tens of nm feature sizes and in large volume. i can barely make 1 full stack device xD anyway whens neuromorphic computing :P
You do a good job describing the benefits of design, packaging and fab working very closely together. Of course a challenge will be design companies concern that their secrets will benefit competitive design groups via the fab companies and fab companies will have the same concern in reverse where a design company works with more than one fab company. Sounds like the industry might best evolve so that design, packaging and fab are all integrated inside one company and these IP Security concerns don’t create barriers. I’ve noticed car companies are integrated. So are hdd companies, spacex etc.
I worked for KLA-Tencor and went to TSMC in 2004 before it gained so much market share going into the fab was not fun because you had to use bunny suits that was shared.😢this is one of the cost saving methods that TSMC used to become so huge in the semiconductor industry
could .3nm process used to make filters of water molecules? like custom to its .267nm size? it would seem simpler to use just 1 input and just aim for uniform size of pores and tubules/vessels? Want more flow, just form bigger? I know crazy tin hat sounding talk, but Im just curious.
Sounds like getting the ingredients together for a meal, then letting A.I. (Artificial Incompetence) prepare the items? Maybe we should leave it to the A.I. to eat it for us too. Otherwise, ir's all a bit esoteric for moi, this one, I got lost between the initially mentioned varieties of nodes, and the fabbing'. No surprise there though, it's tRICKy here, but love your work! Excellent, as ever!
very good. I've never heard of fins. The 3D version of a MOSFET is new to me, the finFET. Do you ever cover Morris Chung, TSMC's founder & two time president?.
FinFET is a spectacular technological leap for the chip industry. I think FinFET has been added in the syllabus of almost every EEE/ECE colleges/University, but I could be wrong it that regards.
The number of design rules has increased and exploded in complexity over the years. In the last 20 years process technology has shrunk from 130-190nm to 5 nm today. That’s like 1000X transistors in the same sized chip. So when you hear of 100B transistors, that used to be "only" 100M. It’s not that design rules have been ignored, but rather they have increased, greatly, in both number and complexity that fabs now work with designers to allow analysis and trade offs in bending and pushing some of the design rules. Chip industry needs near perfection (99.99999% doesn’t cut it!) on each of the 100’s of billions of transistors or the probability or yield of a working chips would fall to zero very quickly.
I wonder if the trust needed to make design technology co-optimization work contributes the significance of Nvidia asking TSMC if they can scale back orders for Lovelace silicon. I also wonder if the customization of leading edge notes at this point means that it would be particularly difficult to find new buyers for the capacity Nvidia wanted to divest itself of but was unable to due to not finding someone to buy in their stead.
I have a couple of questions that I hope someone can answer. Once processor manufacturing has reached it's physical limit or close to it, well there still be performance improvements for the foreseeable future based on design factors? For instance just architectural improvements that improve performance and efficiency. Also I assume that the next big push will to drastically improve performance per watt. If that is achieved to a significant level, would it be possible to build up the chips with many more layers due to the decreased heat production? Or perhaps fancy lithographic techniques to create tiny cooling channels or something similar? So building upwards instead of outwards a but like the AMD 3D vcache chips. Also, how far can the chiplet design be taken? Hypothetically, if we were to ignore power consumption, could AMD feasibly create CPUs and GPUs with 10? 20? chiplets and increase performance that way? Again, especially if electrical efficiency continues to improve. Basically, are we going to reach a dead end in the near future, or are there lots of insanely clever people coming up with insanely clever ideas to work around the end of transistor density improvements? Also why have GPUs suddenly had these insane performance improvements from one generation to the next, like they just don't care about moore's law? Is that just making bigger chips sucking down more power? Thanks for anyone that can clear it up for me.
My answer to first question, It will probably cost too much to sell, and from now on we may see Jensen's Moore's Law quotes at the Ada Lovelace conference. On the other hand, AMD's soon-to-be-announced RDNA 3 cards may show some bigger-than-expected improvements in efficiency and overall processing power thanks to some new chiplet-based designs. Also for second question , you should check more stories about RDNA 3. Probably they will efficient and more less cost but without shrinking whole design idk how far can they go. This is also big bet for nations ( us , uk , china and more ) and multibillion companies ( Nvidia , Apple , Intel , Google and more ) question.
A good example for your presentation is the definition of a "letter-quality" laser printer. One company took an IBM Selectric typewriter with a new type ball, high-quality bond paper, and a new carbon-film ribbon. Then they typed letters and measured the letters under a microscope. The edges of the letters are never straight. They measured the diameter of the invitations along the edge. They found that "letter-quality" if 400 dpi. Canon introduced the 300 dpi laser head so most of the laser printers were "not-quite-letter-quality". Nvidia is investigating modifying the design to produce the best mask. Of course, the obvious next step is to modify the design to produce the least distorted chip.
Have you done a video on backside power vias? I think it'd be really cool since it's new but also maybe there isn't enough information on the topic just yet
do videos on equipments used for the chip manufacturing, its Bill of materials, technology parts, who manufactures them. Similar to your videos on EUV, ultrapure water, etc.
When you say thermal efficiency, do you mean thermal conductivity? If so, then gate all around (or nano-sheet) jut means the gate will fully surround the channel, it won't necessarily add any additional thermal resistance to the stack. Furthermore, the metal tracks add a lot more height to the die overall. And there's also the IHS that desktop CPUs have. All of those add a whole lot more thermal resistance than anything at the transistor level. CFETs will have more of an affect on that than GAAFETs, but even CFETs shouldn't hurt thermal conductivity much. And consider that this is in an era of advanced 3D packaging where Intel and AMD are stacking SRAM dies on top of CPU dies.
@@AlexSchendel I'm thinking of it from a cost/performance standpoint. I'm unsure of the potential gains between sequential nano-sheet nodes. Unlike FinFET nodes where dimensions are reduced between each generation. Nano-sheet nodes would not have that benefit and would require more sheets to improve the stack performance, which leads me to believe that this would only increase the thermal load of the node and clockspeeds will have to suffer for it. Are you saying that adding more nano-sheets in GAAFETs will not cause much of an issues as far as thermals and would not result in overall lower clockspeeds?
@@将軍九八.彁 Well, stacking them vertically has the obvious area benefit and having taller stacks will certainly improve electrical conductivity across the channel (just like how Samsung says they'll vary the nanosheet width to increase conductivity or save area). And that improved conductivity/reduced resistance means you'll have better thermal characteristics because less energy is lost to heat. Feature sizes should also continue to shrink with GAAFETs, just at a slower rate and it will definitely require an overhaul of feature measurements as the initial GAAFETs are gonna be quite wide compared to current FinFETs.
@@AlexSchendel Thanks. I will be interested to see the node specs when they come out and to see if they can achieve a good price/performance that will make them accessible to the average consumer. I'm unsure of GAA and for me I can't wait to get my hands on some TSMC 3nm chips!
@@将軍九八.彁 yeah! Performance will definitely always be going up. Prices are going to be difficult going forward as wafer prices keep doubling, but between smaller dies, advanced packaging, and improved architecture, the incumbents have found a way forward so far haha.
These videos are fantastic! Would love it if you could do more videos on topics one-level up in the value chain (PCBA design and manufacturing; Foxconn, Flex, Jabil, Zollner etc.)!
i've been binging this semiconductor playlist and i still have no idea what a process node is other than it has something to do with how small things are
Thanks for the great video maybe the 3D IC can get refined enough in the next 5-7 years so that the mainstream chip designs could use the technology more often with less of the challenges it introduces
You’ve gotta dance like there’s nobody watching, Love like you’ll never be hurt, Sing like there’s nobody listening, And live like it’s heaven on earth
I wonder how fabs and chips will look like 30 years from now, or even 100 years from now. Maybe some photon CPUs instead of electricity? Some other material than silicon? Quantum computing?
for desktop computers and other applications that don't care about size as much (unlike cell phones and tablets), why do they need to shrink it down further instead of just making the chip bigger? serious question. Why does it always have to be that 3x3 cm CPU instead of a 15x15cm? if i can get 25x the computational power with the same fab (which translates to cost), i'll take 15x15cm CPU, wouldn't you?
@@teghem6723 Another thought is, how much more can you actually parallelize everything? Even tho if you now have more spaces with smaller transistors you need to use the free space effieciently. We are also limited by Amdahl's law. So there is again a trade off. Is it worth it to have more space for more computational power in exchange for bigger area and hence higher costs?
Shrinking dimensions of transistors and wires reduces power, area and cost. If dimensions can be shrunk 5X in the x and y directions, then a 3x3cm CPU can do what would take 15x15cm, but at close to 1/25th the cost and power. I am not saying 5X shrinkage from here is easy but rather 5X shrinkage has already led to the powerful and cheap phones, laptops, etc. that we have today. In the early 2000’s 130-180nm processes were used. In 2022, 5nm. That’s a 26-36X reduction in one dimension. Squared, that’s a 600-1000X type reduction. Simply huge improvement. It is true that GPUs have been growing in size, as a means of obtaining greater performance. Still, it would be better if Moore’s law type improvements continued so power, cost and performance improvements continue. Cost is proportional to area.
And both sides (foundry & design) must sign over their organs to keep each others' secrets safe. The tight ties between the two is also why it's impossible to just switch foundries (i.e. NVidia can't suddenly switch from using Samsung to TSMC, and vice versa).
Did you already talk about "the death of moore's law" ? That would be interesting. Heard quite some different takes on it, so now I dont know whether to chill or panic.
could you do a video on other attempts to enter the semiconductor supply chain? A vietnamese company FPT just announced launching their own chips manufactured by samsung and I wonder where this fits in the overall industry
Might aswell call it atomic scale feature sizes, u at a point where you pretty much pick, pluck, and place a bunch of atoms and molecules on a piece of silicon
The manufacturers spend billions making the chips more efficient so software engineers can make less apllication software more bloated and resource hungry. In terms of capital it would be much more efficient to keep the current technology node and simply optimise the software.
Since the 80's the software industry gained a huge amount of flexibility by sacrificing a bit of overall performance. This will need a large slowdown in lithography and microarch improvements to make them get backward on coding style. Also when introducing a new feature inside hardware, it takes time to devs to implement it inside stable releases. And even if it's ready in software development, commercial software might need to wait for those hardware optimizations to acquire a major market share to be pushed without making the software incompatible with old systems.
@@noticing33 Yeah gaming is a perfect example as GPUs are very complex beasts nowadays, even considered computers by themselves and heavily relying on drivers and optimizations.
At 3 nm have we hit a similar limit like 2005? I buy a new iPhone 📱 every year because historically it is exponentially better. I did that with laptops from the mid 90’s until 2005 ish. Now I might go five or six years before “needing” a new computer. Thoughts? Are we a similar limit?
When it comes to smartphones, we have hit a plateau. When you look at the iPhone 14 vs 13, it's is only incrementally better. The same could be said about iPhone 13 vs 12. I think this also applies to iPads. They are all mature technology now.
We are coming to the end of an era below 5nm. Things get extremely complicated, cost get extremely high at 3nm. At 2 or 1 nm, well it's impossible. Say who? Say quantum physics. Therefore it is better to put research money into stacking the chips. Stack two 5nm chips and you get the rough equivalent of a 2.5nm performance at 5nm complexity. In theory. Of course stacking has huge challenges but invest in this is better than invest in ever finer geometry because nobody can change quantum physics. Those who solved stacking create a new technology, new chip industry. Keep Moore's law going and command the tech world. So who can achieve this? China. It has the brains and money, the motivation. What about TSMC - for sure but it has invested so much in current node tech it is hard to start something new. Samsung - unlikely but a reasonable chance. What about U.S.? Forget about it. Intel can't even do 10nm in reliable mass production after years of trying. And they can buy all the litho machine they want. They just don't have the brain power anymore.
I dont get it how can you keep going without reward like without monetizing it etc. Like also knowing youtube favors lower quality shorter videos a lot of times too so. Not complaining cause god damn bro
Maybe what is needed is a split into three: product design library design process design Someone will have to restrict and manage all the options at a cell level.
As long as your nodes are for inherently quantum mechanically defective CMOS circuits. Electrons and holes propagate at different speeds. This creates a transient short from power to ground once each clock cycle. For GaN, the difference is even greater creating larger spikes. Resonant tunnel diode threshold logic does not have this problem. But it would require their "experts" to actually learn something new. Threshold Logic alone would reduce the gate count by 30% because a Threshold Logic Gate has more computing power than Boolean Logic. And Neural Networks can easily compute the weights and thresholds needed to synthesize the functions. It is also trivial to synthesize threshold logic gates using tunnel diodes. But all this would require "engineers" to actually learn something after graduating. I saw this problem at TI, trying to get "engineers" to move from TTL gates to I²L gates.
How you keep cranking out such informative videos on complex specialized subjects blows my mind.
I wish he would post his sources.
He worked in industry
Exactly, I have a deep experience in the field and am super impressed by the depth and breadth of the knowledge he drops in each and every video. The part I can't figure out is how he does it so fast. Truly gifted at this.
@@theianmce Good time management goes a long way
@@MJ-uk6lu
That _would_ explain a _lot._
I'm still impressed.
I am consistently amazed by the amount of quality information in your videos. Keep up the good work.
YES!
I recently found out that costa rica has a pretty big semiconductor industry, I find it to be very odd choice for such an industry focused mostly in east asia and the USA. A video on that would be very interesting imo
Yeah, it's Post fab assembly, packaging and tests.
7:08 DTCO - Design Technology Co-Optimization. That is a really important concept in semiconductor design and manufacturing, and can be applied in a lot of other industries as well.
DTCO is a fancy term for talking to the client, and is a crutch solution.
While talking to the client is still necessary, and beneficial, it can and should be reserved for edge cases and critical design and wisdom, not holding their hand through the rote basics.
The fabs could have categorized and tagged each rule better as required, optional, and quantifying what the tradeoffs are for the optional ones.
Then they could make all this cataloguing searchable and self-explained via a simple web app, where the chip designers can reference, search, filter, sort rules easily by tag, and the quantified tradeoffs can be presented in a straightforward manner.
Then DTCO can focus on the questions that really matter, and be a source of feedback, which continually gets incorporated into improving the web app for more rules, deprecating rules, etc.
Love this video and so many of the ones you make. This video has a lot of call backs to older videos you make. If you reference a video, could you also link it in the description? Would make it a lot easier to bounce over to that video for context and then bounce back when done. Keep up the great work!
I work in the industry and these videos teach me a lot.
Xilinx was known for their incredibly tight relationship with TSMC. AMD, having owned their own fabs previously, was already intimate with working directly with the lithography department, so they quickly ascended the same stairs with TSMC. Today AMD owns Xilinx, and it is speculated that their ultimate goal is to beat Apple to the leading edge and become the premier partner of TSMC. If that happens I think both Intel and Nvidia will be in long term trouble...
Doesn't premier partner status in this relationship have more to do with wafer purchases than engineers?
Apple has a market cap 23 times AMD's. just say'n
but apple had tremendous amount of cash on his pocket (yeap real reserve cash from sellin iphone) they can buy all new tsmc node volume like 100% all off it production year long
I speculate that you’re talking out your ass lol. Idk how you think the tiny Xilinx arm of amd is going to displace Apple. Not unless Apple decides to build their own fabs 😂
@@zunriya what it depends on is if Apple stops innovating like they did t with the iPhone 14, they reuse the same old chip as last year, only updating the iPhone Pro. If competitors don't catch up they will likely not push the bleeding edge as hard
This past week I was reading your article on the Perkin-Elmer blog.
Very well done! Thanks for making it so approachable for those who might not be in the field. 👍
So true.
Relegated to produce pumps?
@@ntabilePerkin Elmer?
Perkin Elmer started in optics.
Creating telescopes, bomb sights and the optics of spy satellites, by the late '60's they had military contracts to fab semiconductors and by the mid '70's were selling the Micralign projection system.
This semiconductor division got sold to SVG and ultimately became ASML Wilton.
They were also deep into analytical lab equipment and pioneers of PCR with their genomics division.
There was a lot of micro fluidics and chromatography going on, so I guess 'pumps' in a way...
"It's like haggling at a Taiwan night market" brought back wonderful memories of a visit to Kaosiung some time ago. But now I'll have to watch this one again after writing down the acronyms. I want to savor the details and Google search some of the principles. Also want to see how they apply to GPUs and the special chips coming out for AI research. Interesting stuff....
Cheers!
I suspect that AI is in it's early infancy and that in 5 - 10 years this time of AI computing will seem extremely archaic. Will Nvidia be seen as a leader of AI in 10 years or an extinct dinosaur
I want the spicy chicken chop at Shilin Market!
Your mention of Acronyms, brought me a Chuckle. When I Worked at Intel, and Attended Meetings, I was overwhelmed by the Acronyms.
At next Meeting, I was Handed an Intel Acronym Dictionary, LOL.
Best cutting edge & historical chip technology + unrelated interesting subjects all in one place?
Well done!
Great Video. I am very stunned to know the technicalities behind the chip design, Thank you so much for this video. All your videos about TSMC / chip making makes me feel like working on chips :)
I think it’s worth repeating that I have zero idea how any of this stuff works, but that I’m totally captivated by these videos. Very informative, but I have no idea what the information is😅
At 1:58 shoudn't it be the other way around? That the wavelength of the light was smaller than the feature size? I assume that you need wavelengths smaller than the feature size you're etching or am i missing something
Love your content man. If you ever come to Australia I’d attend any type of talk you could get going, or just grab you a drink!
Thank you, thank you, thank you! It'd the best overview of the history of the chip design process. I'm wondering if you could compare ASMC and Intel design processes. Such a video would be extremely interesting! I would highly appreciate such a comparison!
Thanks!
as someone in university labs working on 300nm EBL. its insane to think about how these people are making tens of nm feature sizes and in large volume. i can barely make 1 full stack device xD
anyway whens neuromorphic computing :P
Love your documentaries! Is it possible to cover about X-rays lithography? It would be interesting to compare it with current EUV process.
You do a good job describing the benefits of design, packaging and fab working very closely together. Of course a challenge will be design companies concern that their secrets will benefit competitive design groups via the fab companies and fab companies will have the same concern in reverse where a design company works with more than one fab company. Sounds like the industry might best evolve so that design, packaging and fab are all integrated inside one company and these IP Security concerns don’t create barriers. I’ve noticed car companies are integrated. So are hdd companies, spacex etc.
I worked for KLA-Tencor and went to TSMC in 2004 before it gained so much market share going into the fab was not fun because you had to use bunny suits that was shared.😢this is one of the cost saving methods that TSMC used to become so huge in the semiconductor industry
amongst all the video here this is the best and one of the most informative and important
Cooperation once again showing its strengths at the leading edge.
My 3nm process involves a sweatshop full of workers with tiny tweezers, chisels and eyedroppers.
Yeah, the yield is crap, but we are expanding our incentive program to include things like food and water.
That's their government to blame for allowing such horrendous working conditions.
Well explained....I need to learn more to get to grasp all the details here.
could .3nm process used to make filters of water molecules? like custom to its .267nm size?
it would seem simpler to use just 1 input and just aim for uniform size of pores and tubules/vessels?
Want more flow, just form bigger?
I know crazy tin hat sounding talk, but Im just curious.
Sounds like getting the ingredients together for a meal, then letting A.I. (Artificial Incompetence) prepare the items? Maybe we should leave it to the A.I. to eat it for us too. Otherwise, ir's all a bit esoteric for moi, this one, I got lost between the initially mentioned varieties of nodes, and the fabbing'. No surprise there though, it's tRICKy here, but love your work! Excellent, as ever!
very good. I've never heard of fins. The 3D version of a MOSFET is new to me, the finFET. Do you ever cover Morris Chung, TSMC's founder & two time president?.
FinFET is a spectacular technological leap for the chip industry. I think FinFET has been added in the syllabus of almost every EEE/ECE colleges/University, but I could be wrong it that regards.
Every industry has principles of "design for manufacturability". I'm surprised to hear chip designers were able to ignore theirs for so long!
The number of design rules has increased and exploded in complexity over the years. In the last 20 years process technology has shrunk from 130-190nm to 5 nm today. That’s like 1000X transistors in the same sized chip. So when you hear of 100B transistors, that used to be "only" 100M.
It’s not that design rules have been ignored, but rather they have increased, greatly, in both number and complexity that fabs now work with designers to allow analysis and trade offs in bending and pushing some of the design rules.
Chip industry needs near perfection (99.99999% doesn’t cut it!) on each of the 100’s of billions of transistors or the probability or yield of a working chips would fall to zero very quickly.
My brain suffers a bluescreen just thinking about the insane complexity of all of this.
A good question to ask TSMC and Samsung is how many suicides and death by overwork they have.
More and more processes in the same level is a clear sign that we soon run into the next wall and new big changes are needed to overcome that again.
I wonder if the trust needed to make design technology co-optimization work contributes the significance of Nvidia asking TSMC if they can scale back orders for Lovelace silicon.
I also wonder if the customization of leading edge notes at this point means that it would be particularly difficult to find new buyers for the capacity Nvidia wanted to divest itself of but was unable to due to not finding someone to buy in their stead.
Will you talk about RF/analog and other specialty nodes? And what about III-V semiconductors?
Would you add more podcasts to Spotify? I don’t get service in the fab and I want to learn while working!
Hi, have you though of creating an explainer for the upcoming Gate All Arround transistors?
I have a couple of questions that I hope someone can answer. Once processor manufacturing has reached it's physical limit or close to it, well there still be performance improvements for the foreseeable future based on design factors? For instance just architectural improvements that improve performance and efficiency. Also I assume that the next big push will to drastically improve performance per watt. If that is achieved to a significant level, would it be possible to build up the chips with many more layers due to the decreased heat production? Or perhaps fancy lithographic techniques to create tiny cooling channels or something similar? So building upwards instead of outwards a but like the AMD 3D vcache chips. Also, how far can the chiplet design be taken? Hypothetically, if we were to ignore power consumption, could AMD feasibly create CPUs and GPUs with 10? 20? chiplets and increase performance that way? Again, especially if electrical efficiency continues to improve.
Basically, are we going to reach a dead end in the near future, or are there lots of insanely clever people coming up with insanely clever ideas to work around the end of transistor density improvements?
Also why have GPUs suddenly had these insane performance improvements from one generation to the next, like they just don't care about moore's law? Is that just making bigger chips sucking down more power?
Thanks for anyone that can clear it up for me.
My answer to first question,
It will probably cost too much to sell, and from now on we may see Jensen's Moore's Law quotes at the Ada Lovelace conference. On the other hand, AMD's soon-to-be-announced RDNA 3 cards may show some bigger-than-expected improvements in efficiency and overall processing power thanks to some new chiplet-based designs. Also for second question , you should check more stories about RDNA 3. Probably they will efficient and more less cost but without shrinking whole design idk how far can they go. This is also big bet for nations ( us , uk , china and more ) and multibillion companies ( Nvidia , Apple , Intel , Google and more ) question.
"Plenty of room at the bottom", if it's the QM cause-effect Infinity-Singularity Reciproction-recirculation focus of AM-FM point-line-circle = specific zero-infinity location-> line-of-sight/horizontal-> vertical integration inside-outside holographic quantization positioning presence "Circuitry" of QM-TIME Completeness-> Reciproction-recirculation cause-effect=> Unity @ zero-infinity sync-duration, infinite scale Fluxion-Integral Temporal superposition Calculus .
Interesting video thank you.
Really enjoy learning from you
A good example for your presentation is the definition of a "letter-quality" laser printer. One company took an IBM Selectric typewriter with a new type ball, high-quality bond paper, and a new carbon-film ribbon. Then they typed letters and measured the letters under a microscope. The edges of the letters are never straight. They measured the diameter of the invitations along the edge. They found that "letter-quality" if 400 dpi. Canon introduced the 300 dpi laser head so most of the laser printers were "not-quite-letter-quality".
Nvidia is investigating modifying the design to produce the best mask. Of course, the obvious next step is to modify the design to produce the least distorted chip.
Curious as to when it will be cost/time effective to use e-beam lithography instead of photolithography.
Have you done a video on backside power vias? I think it'd be really cool since it's new but also maybe there isn't enough information on the topic just yet
Just want to thank you for all the great videos 😃
That was a wonderful and educational video. Thank you.
Great video. Do you personally work in the semiconductor industry?
do videos on equipments used for the chip manufacturing, its Bill of materials, technology parts, who manufactures them. Similar to your videos on EUV, ultrapure water, etc.
Do you think nano sheet nodes will have thermal efficiency issues?
When you say thermal efficiency, do you mean thermal conductivity?
If so, then gate all around (or nano-sheet) jut means the gate will fully surround the channel, it won't necessarily add any additional thermal resistance to the stack. Furthermore, the metal tracks add a lot more height to the die overall. And there's also the IHS that desktop CPUs have. All of those add a whole lot more thermal resistance than anything at the transistor level. CFETs will have more of an affect on that than GAAFETs, but even CFETs shouldn't hurt thermal conductivity much. And consider that this is in an era of advanced 3D packaging where Intel and AMD are stacking SRAM dies on top of CPU dies.
@@AlexSchendel I'm thinking of it from a cost/performance standpoint. I'm unsure of the potential gains between sequential nano-sheet nodes. Unlike FinFET nodes where dimensions are reduced between each generation. Nano-sheet nodes would not have that benefit and would require more sheets to improve the stack performance, which leads me to believe that this would only increase the thermal load of the node and clockspeeds will have to suffer for it. Are you saying that adding more nano-sheets in GAAFETs will not cause much of an issues as far as thermals and would not result in overall lower clockspeeds?
@@将軍九八.彁 Well, stacking them vertically has the obvious area benefit and having taller stacks will certainly improve electrical conductivity across the channel (just like how Samsung says they'll vary the nanosheet width to increase conductivity or save area). And that improved conductivity/reduced resistance means you'll have better thermal characteristics because less energy is lost to heat. Feature sizes should also continue to shrink with GAAFETs, just at a slower rate and it will definitely require an overhaul of feature measurements as the initial GAAFETs are gonna be quite wide compared to current FinFETs.
@@AlexSchendel Thanks. I will be interested to see the node specs when they come out and to see if they can achieve a good price/performance that will make them accessible to the average consumer. I'm unsure of GAA and for me I can't wait to get my hands on some TSMC 3nm chips!
@@将軍九八.彁 yeah! Performance will definitely always be going up. Prices are going to be difficult going forward as wafer prices keep doubling, but between smaller dies, advanced packaging, and improved architecture, the incumbents have found a way forward so far haha.
These videos are fantastic! Would love it if you could do more videos on topics one-level up in the value chain (PCBA design and manufacturing; Foxconn, Flex, Jabil, Zollner etc.)!
Would a company like Apple be able to buy tsmc outright?
anti-monopoly laws should stop that
i've been binging this semiconductor playlist and i still have no idea what a process node is other than it has something to do with how small things are
Can you do the leading edge manufacturing video about the philippines? I heard their largest export are leading edge circuitry
Thanks for the great video maybe the 3D IC can get refined enough in the next 5-7 years so that the mainstream chip designs could use the technology more often with less of the challenges it introduces
When you said multiverse, couldn’t help but think even TSMC wants to create their own version of MCU
Top video as usual
You’ve gotta dance like there’s nobody watching,
Love like you’ll never be hurt,
Sing like there’s nobody listening,
And live like it’s heaven on earth
More about 3nm process node.
Less about history of older process nodes.
I am only a dreamer.
What is Atomera trying to do?
this video is really really good
I wonder how fabs and chips will look like 30 years from now, or even 100 years from now. Maybe some photon CPUs instead of electricity? Some other material than silicon? Quantum computing?
for desktop computers and other applications that don't care about size as much (unlike cell phones and tablets), why do they need to shrink it down further instead of just making the chip bigger? serious question.
Why does it always have to be that 3x3 cm CPU instead of a 15x15cm? if i can get 25x the computational power with the same fab (which translates to cost), i'll take 15x15cm CPU, wouldn't you?
If you can make features smaller then you can fit more transistors on the same size chips so more powerful computers.
i don't think you can achieve the same frequency in the bigger chips
Think about the processed wafer size and cost!
@@teghem6723 Another thought is, how much more can you actually parallelize everything? Even tho if you now have more spaces with smaller transistors you need to use the free space effieciently. We are also limited by Amdahl's law. So there is again a trade off. Is it worth it to have more space for more computational power in exchange for bigger area and hence higher costs?
Shrinking dimensions of transistors and wires reduces power, area and cost. If dimensions can be shrunk 5X in the x and y directions, then a 3x3cm CPU can do what would take 15x15cm, but at close to 1/25th the cost and power. I am not saying 5X shrinkage from here is easy but rather 5X shrinkage has already led to the powerful and cheap phones, laptops, etc. that we have today.
In the early 2000’s 130-180nm processes were used. In 2022, 5nm. That’s a 26-36X reduction in one dimension. Squared, that’s a 600-1000X type reduction. Simply huge improvement.
It is true that GPUs have been growing in size, as a means of obtaining greater performance. Still, it would be better if Moore’s law type improvements continued so power, cost and performance improvements continue. Cost is proportional to area.
4:36 no PPAP meme?
And both sides (foundry & design) must sign over their organs to keep each others' secrets safe.
The tight ties between the two is also why it's impossible to just switch foundries (i.e. NVidia can't suddenly switch from using Samsung to TSMC, and vice versa).
I hope nvidia goes to ...... you know the place
Awesome video thanks
Nice vid, more ASML content please!
Did you already talk about "the death of moore's law" ? That would be interesting. Heard quite some different takes on it, so now I dont know whether to chill or panic.
Some do not get that nothing lasts forever.
I actually enjoy your videos, even if sometimes misleading. Honestly, I eagerly sponge up every episode immediately. Thank you for the media. 👍
could you do a video on other attempts to enter the semiconductor supply chain?
A vietnamese company FPT just announced launching their own chips manufactured by samsung and I wonder where this fits in the overall industry
Please make a video about UMC.
this video... business, technology, geopolitics, economics all rolled into one.
That TSMC facility at 40sec looks like the McLaren F1 factory in the UK.
Might aswell call it atomic scale feature sizes, u at a point where you pretty much pick, pluck, and place a bunch of atoms and molecules on a piece of silicon
The manufacturers spend billions making the chips more efficient so software engineers can make less apllication software more bloated and resource hungry. In terms of capital it would be much more efficient to keep the current technology node and simply optimise the software.
there's a big inertia in software industry
Since the 80's the software industry gained a huge amount of flexibility by sacrificing a bit of overall performance. This will need a large slowdown in lithography and microarch improvements to make them get backward on coding style.
Also when introducing a new feature inside hardware, it takes time to devs to implement it inside stable releases. And even if it's ready in software development, commercial software might need to wait for those hardware optimizations to acquire a major market share to be pushed without making the software incompatible with old systems.
That's sucks, a bit like how some games perform so badly on great GPUs and othegames perform twice as good even tho visually they're just as good
@@noticing33 Yeah gaming is a perfect example as GPUs are very complex beasts nowadays, even considered computers by themselves and heavily relying on drivers and optimizations.
....isnt the current from source to drain ??
At 3 nm have we hit a similar limit like 2005?
I buy a new iPhone 📱 every year because historically it is exponentially better. I did that with laptops from the mid 90’s until 2005 ish. Now I might go five or six years before “needing” a new computer. Thoughts?
Are we a similar limit?
When it comes to smartphones, we have hit a plateau. When you look at the iPhone 14 vs 13, it's is only incrementally better. The same could be said about iPhone 13 vs 12. I think this also applies to iPads. They are all mature technology now.
why buy iphone at all?
This is super interesting.
I pledge not to skip ahead when you "plug" your newsletter.
I wish it was more. . . . they are awesome videos...
Keep well and hope to see some of Taiwan myself soon meeting the in-laws in Taipei.
Buy you some bubble tea or coffee at a market?
What would Moore think?
100 views in 10 seconds 👍
8:08 electrical engineering in 3 seconds
DTCO at TSMC for PPAC!
MediaTek 3nm chip is expected to offer better gaming performance
Does it mean that onboarding new customers onto the currently leading edge node is going to be a spectacularly complex and prolonged endeavour?
So 2030 is the era of 1nm to 500 pm (Picometer)?
After seeing tsmc 5nm performance
But I don't see 3nm would be anywhere better than Intel 4
hey i would like you to make more videos about electric cars. and everything related to it.
What's wrong with corners that are not sharp? And what the hell happened to "X" architecture?
We are coming to the end of an era below 5nm. Things get extremely complicated, cost get extremely high at 3nm. At 2 or 1 nm, well it's impossible. Say who? Say quantum physics. Therefore it is better to put research money into stacking the chips. Stack two 5nm chips and you get the rough equivalent of a 2.5nm performance at 5nm complexity. In theory. Of course stacking has huge challenges but invest in this is better than invest in ever finer geometry because nobody can change quantum physics.
Those who solved stacking create a new technology, new chip industry. Keep Moore's law going and command the tech world. So who can achieve this? China. It has the brains and money, the motivation. What about TSMC - for sure but it has invested so much in current node tech it is hard to start something new. Samsung - unlikely but a reasonable chance. What about U.S.? Forget about it. Intel can't even do 10nm in reliable mass production after years of trying. And they can buy all the litho machine they want. They just don't have the brain power anymore.
Cover MICRON Technology in TAIWAN
"Cost" might be the more technically correct term, but I can't help but feel that it's a bit of a shame they didn't go with "Price" instead
I dont get it how can you keep going without reward like without monetizing it etc. Like also knowing youtube favors lower quality shorter videos a lot of times too so. Not complaining cause god damn bro
Not so sad 😱
Simply because you don't actually understand or know of the process or its history doesn't make it "simple"
Ohio is getting the new one. It’s going to get really wild….
Soon they no longer can go farther! It is physics limitation
I heard that there were already 1nm prototypes
There’s no need to jump to 1nm. AMD 5nm/6nm chiplets can beat Intel monolithic 3nm. 3D V-cache is already causing panic at Intel AMD Nvidia.
@@tringuyen7519 intel is moving to chiplets soon tho
I'm honestly eager to see what they are going to do from there, and if there's gonna be some sort of breakthrough
Maybe in 20 years. There is still a lot known of scaling potential in many dimensions and methods.
Maybe what is needed is a split into three:
product design
library design
process design
Someone will have to restrict and manage all the options at a cell level.
Instant like
outstanding content ! .. thanks !
5:33 that is a sweet curve indeed 😍
As long as your nodes are for inherently quantum mechanically defective CMOS circuits. Electrons and holes propagate at different speeds. This creates a transient short from power to ground once each clock cycle. For GaN, the difference is even greater creating larger spikes. Resonant tunnel diode threshold logic does not have this problem. But it would require their "experts" to actually learn something new. Threshold Logic alone would reduce the gate count by 30% because a Threshold Logic Gate has more computing power than Boolean Logic. And Neural Networks can easily compute the weights and thresholds needed to synthesize the functions. It is also trivial to synthesize threshold logic gates using tunnel diodes. But all this would require "engineers" to actually learn something after graduating. I saw this problem at TI, trying to get "engineers" to move from TTL gates to I²L gates.
3nm chips.