Agreed, this channel is legendary. So much insight on what the industry's doing, and still explained clearly (or as much as it can be on those topics) Thanks for your work!
I went to a candid talk by someone from Intel back in 2012 and she talked very clearly about the challenges of going into EUV and the impossibility of it with the kind of lasers you need to *actually* get that feature size. I was surprised to find out over the years to see these headlines claiming that companies hit 14nm, 10nm, etc., when I know from my chemistry background just how difficult it is to get that kind of half-width level. I'm surprised how difficult it is to learn the truth about what they're actually doing on the etching level without an explanation like this. Thank you for shaking me out of the stupor of years of marketing to see the truth that chip designers have been "cheating the barrier" to keep up with feature density growth. This also explains why yields for everything, from PS5s to the M1s, are so terrible these days...
@@graficeb3484 EUV reduces the layers required vs. DUV-only lithography, so theoretically, EUV is easier. Playstation V's SoC (TSMC 7nm - N7p or N7+) is sizable 308-square mm die. Apple's M1 is on TSMC N5, which has better yields vs. N7. It takes a while to perfect the process node. Newer processes will have worse yields. Due to production issues, TSMC had to delay its N3 node, which was supposed to be ready by mid-2022 for Apple A16 Bionic for iPhone 14. Also, Samsung is facing delays to their 3nm GAA node. The shrinking nodes are getting harder and harder to launch on time for commercial production. If the chip is smaller (less defects per square millimeter), the yields are better, which is why AMD's CCX dies are primarily cores and cache. It was rumored that AMD's Zen II CCX dies had 70% yield on TSMC's 7nm process when production started. With time, TSMC figures out how to reduce defects and implements the fixes. Allegedly right now, TSMC's 7nm class nodes have statistically perfect yields. TSMC has a reputation of being the fastest to improve yields versus Samsung.
To get where you need to be with non EUV lithography means that you have to use "tricks" to shrink down the linewidth. What this functionally means at the 10nm± sizing is that larger lines are printed over various films, these are then etched to give a line that is your starting point. Next you use the fact that you can deposit very thin films very accurately to deposit a thin film over the line (#1) that you then etch to leave a spacer (#1) which is narrower than the line you can print. You can then remove the original etched line material, but leave the spacer; you then use this spacer (#1) as the mask for etching another lower film to produce another line (#2), and repeat the spacer dep/etch/remove line(#2) process. Finally you etch the last layer of material to produce you final desired lines. This is "quad patterning" and it allow you to reduce the size of your lines, because you use the spacers as the mask for the etching, the size of these is not limited by optics. You also reduce the pitch of your lines (ie distance between lines) because you have the spacer on each side of the line you use to make the spacers, again this "gets round" the optical limits of UV print. The downside of this is increased process complexity, restrictions in patterning, additional processes to "cut" lines as printing line ends increases issues. Multiple layers to be deposited/etched. This all adds up to process time, complexity, and defects, because more steps means more defects, and hence lower yield. If you have EUV, you can do a print/etch without playing tricks which is so much faster....and saves defects. look at this www.monolithic3d.com/blog/the-quad-patterning-era-begins for a visualisation of the above. Note: this is a simplified view...
@@worldtownfc If a die is smaller then yield is better for a given defect density as p(defect in die area) is lower. If defect density is lowered you have the same impact, but from the opposite direction. You can also increase yields if you have built in redundancy to the design, such that you can "replace" an area with a defect with the equivalent circuitry in another area - this makes the die bigger, but it can improve yield more than reduced # of die on the wafer & hence reduce costs. If you make your die on optimised processes for each function, as AMD has done, then you increase die yield due to smaller areas - you can tolerate a defect density more than larger die. Also the variation across a die will be smaller, as it takes up less of the print field, which may improve die yield if timing skews are critical or bin splits. It also allows better matching between speeds/voltage requirements of the chiplets. BTW, unless they have changed, TSMC do not give a monkey's about your yield (they sell you wafers that meet certain criteria, not yield), as long as they meet the defect density they say they will and the electrical results they say they will. If your device has sensitivities to the process it is usually up to you to sort out your design, not for TSMC to tweak the process.
it's funny to think about the time when they were underpromising and over delivering, back when they first broke from the convention of "process node" = "actual gate length". In 1997, intel's 250nm process had a gate length of 200nm. later on it got "worse" with a 135nm process that had an actual gate length of 70nm. Now it's swung the other way. their 10nm process has 18nm gate length. From an almost 2x buffer to an almost 2x deficit.
This was really well done, as an instructor, I especially appreciate his humbleness to attempt to explain things he doesn't fully understand, and to do it in a way that inspires curiosity without superimposing arrogance. The description of the fuzziness around node technology is especially useful in deciphering both the history and evolution of this very complex intersection of technologies.
2 года назад+26
That was a hell of a explanation man, I'm really happy that I've found your Channel. Keep up the exelent work.
Very informative yet understandable. A new gold standard for RUclips videos. Highly interesting to see some of what's going on in chip technology. I always wondered why current chip designs looked much neater than older designs. Now I know.
The big reason that Intel struggled so much with the N10 and N7 nodes was etch yields. Since they had to do the crazy multipatterning etch defects would creep in and yield plummeted. Their etch vendors had to advance their tech to achieve acceptable yields. Once they did they have been ramping production to meet the backlog of orders ever since. And yes I am in the industry so I know this to be true.
I used to work in a semicon mfg and assigned at backend- moulding and dtfs area. I was not not able to take a peek at frontline on how dies are dice and wire bonded. Reading and viewing your vlog about process how the billion of transistors are made in a wafer and the technology involved in doing this really amaze me.
I love the research and pictures you put into this to explain it. I used to have occasional magazine articles with this type of info to read. Those aren't really around anymore. This is great quality.
With every view, you’re honest to God teaching one more additional industry professional an insane amount of information about the industry they’re actively in. You’re likely doing more for the industry than you think. 🥰
I didn't know anything about semiconductor technology until I found this channel. And you have tought me so much!!! This episode is frying my brain a little. I'm still processing the info, after watching a few times 😁😁😁
This is one channel i love for the content, but also for the extremely brief patreon plug, blink and you'll miss it, and that suits me just fine!! He says what he needs to in order to make us aware, and nothing more. Perfect, just perfect.
Being one who work in this field, I commend you on this video! Awesome job.... but you pronounced Calibre in a strange way.... I teach Calibre applications for a living, so I kinda got hung up on that.
Terrific video as usual. I always wondered why further immersion wasn’t considered, there are certainly higher n materials than those liquids predominantly used in immersion. Anyway it’s moot now since EUV saved the day.
All materials have to be compatible with the other materials that are being used within the process and not add extra complexity or have problems with purity etc...
lmao I work in Lithography. The terminology is absurd. It makes more sense when you realize the scope/scale of the fabs and how everything has to be organized, but yeah it's funny.
@@CRneu I lost my badge access from Intel for making such comments... But I got to do some really cool shit internationally, 3rd party. Anyways... be careful.
The only company that was able to develop a so-called "7nm" node without EUV has been Intel (Previously called Intel "10nm", now called "Intel 7"). You might be tempted to think that this is a great achievement for Intel, however it's actually their biggest blunder. Intel's decision to attempt developing Intel 7 without EUV by heavily relying on aggressive multi-patterning was the main reason they fell behind TSMC by 5-6 years (They were previously 2-3 years ahead of TSMC but now they are 3 years behind).
I agree with you. Intel 10nm era is such a disaster for intel. 10nm nodes from intel will never get intel back to the leadership despite intel released 3 revision to this node (10nm+ with ice lake, 10SF with tiger lake, and intel 7 with alder lake). But i still admire their enermous hardwork to make it work.
You are correct that Intel messed up on the transition to EUV, they held the orders for the first tools, but gave them up (which were then picked up by TSMC). I'd say the real issue here isn't size, rather EUV makes it easier to do more complicated gate designs (think GAA). WRT Intel yield problems at 10nm, vs AMD, I think that AMD were very smart to move to the chiplet approach, this allowed for better yields on poorer defect densities + using appropriate processes for different chiplets. (They got to have their cake and eat it). Intel continued with monlithic chips, which yield lower because of area. Hopefully Intel does have a big order in for EUV systems, they need it, even if they order more than initially seems required, they could back fill "larger node" fabs with streamlined process flow to make yields better and gain experience on EUV, together with priming them for smaller node transition, depends on rate of tool delivery vs orders and speed of new fab ramps. Not sure who gave up the EUV order, maybe Otellini, maybe Kryzanic, I do believe that they missed out on the growth of the foundries - Intel was it a good position to use their older process nodes and fabs as foundaries, that would bring in extra revenue, but more importantly starve the other foundries of some income. They started on it, but very half heartedly, this also saw a major growth and transition of IC production east to Taiwan etc. I am optimistic with Gelsinger at the helm. He is of the same cloth as Grove, Barrett and Moore, though probably more like Grove. I am hopeful that he will also grow a foundry business too.
One thing I would consider here is that because of the DUV hardships you mention, Intel has a huge pipeline of innovation outside of the litho process specifically to make sure the pluses always actually were pluses. Meaning that when the DUV choke point is gone, Intel has an astounding amount of R&D that will separate itself from the pack. When EUV tools essentially are barriers for entry, they also become the floor of achievement for each foundry. The other innovations will decide the winners at that point. Will be interesting to see how much of Intels R&D portfolio is awoken when EUV nodes are fully the norm.
@@thecraggrat Intel had pretty big blunders due to terrible leadership, they were way too focused on finances than on the RND side of the company. There was a massive layoff of smart people "brain drain" which caused the decline of intel. Gelsinger currently rehired those retired people, so it might get better.
@@jakejakedowntwo6613 Ask yourself where intel 7nm is? They don't even hype it anymore, b/c it's so far away from actual production. It's another 10nm failure. Inside sources have been saying this for a long time, too. Intel is slowly admitting it. Their latest xeon roadmap (which we all know every intel roadmap that goes out longer than 6 mo is a lie), show 7nm for end of 2024 LMAO. Expect the lies to continue till you get nearer and that slips even further.
Jon, you cheeky fella, you had me cracking up a couple of times with your remarks, it makes this video all the more worthwhile to watch, aside from the info and insights you provide.
Man I cannot find the right words to express my gratitude and salute to you. This video, as well as many others in the channel, provides a remarkable lot of knowledge to us. You deserve much better attention in RUclips in my honest opinion.
Very good as always. The video finally explained to me why Intel struggled for so long with N10. Amazing technology that advances so quickly, albeit with some steps and ramps. I had read that China has some new technology that bypasses the need for ELV but I have not seen any details.
this video kind of talks about that, it is possible but not practical. However China can probably get away without EUV for a while for most applications. I bet ASML and others are trying to come up with solutions that don't incorporate US IP too as US already talks about putting DUV on the list.
With how unbelievably complex and interesting computer science is, primary schools need to be doing a lot more than just teaching code. Code isn't for everyone. However, insight into how math and science is applied into engineering these vastly important chips seems fundamentally important going forward.
I saw a compelling presentation once called “28nm forever” basically it made the case that the most cost efficient cheapest chips to produce would be 28nm (or let’s stretch to 22?) for a long long time if not perhaps eternity.
Not only is 28nm cost effective in production. It is basically also the end of power and voltage scaling. After that there are more transistors per area, but the transistors use the same power, so the ocerall power per area inceeases.
@@_TeXoN_ I don’t think I agree with you there, otherwise the R5 5600X would not be 65W for it’s performance. I’m not calling you out, I suspect there was some real academia saying this but my gut tells me it can’t be true judging by efficiency gains (per unit of performance or per # of transistors) that we have seen empirically.
@@depth386 Just read about Dennard Scaling. It is the physical equivalent to Moore's Law, but failed around 2005. Everything below 28nm is also not a real measurement, but marketing names.
@@_TeXoN_ Okay I will look into that, and I do agree that “#nm” has become BS, Der8auer showed a 9900K and some Ryzen 3000 ground down to expose to die under an electron microscope, they were almost the same despite “14+++ vs 7”. However, I am left with one more good question. Could you please explain to me, how are they packing more and more transistors? Transistor counts for both GPUs and CPUs are still going up by large percentages comparing one generation to the next. RTX 4000 series graphics cards are rumored to have 3x the 3000 series for instance. A little bit might be die size (and the recent trend of upward creep in power consumption) but there is still much progress in how many transistors they’re etching.
@@_TeXoN_ by the way I just read the wikipedia article on Dennard scaling. It’s not super in depth but it did give me an “aha, so that’s why i noticed going from Pentium 4 2.6Ghz to only 3.06Ghz i7-950 was like.. wtf? There were IPC gains and multi core gains but still, I was used to specs going up like 80386 33Mhz Pentium 1 133 Mhz Pentium 2 350Mhz Pentium 3 1Ghz Pentium 4 2-3Ghz it was tripling even without IPC advancements in the good old days
The best channel ever in RUclips to get yourself educated in semiconductor industry and anything related to high techs 🔥🔥👌.. insanely detailed information 🤯.. It's free MIT level courses🤩.. Never missed a video..always waiting for more.. Thanks for the the extremely good work 😚😚
Another absolutely fantastic video: You’re one of the few channels where I watch every video from start to finish, as soon as I see them :-) Holy moley, though: *Hexa” patterning? That must have had yield ~~0 😮 I was confused in this video by the illustration of the “spacer” layer. I was expecting the etching to happen where the spacer layer *wasn’t”, but it instead seemed to occur where it was present. Did I misunderstand or was that a graphical typo? Thanks as always for the fantastic content; I can’t imagine how you find time in the day just to research and read the source material, let alone record and edit the videos themselves! 🤯
Sorry for dubbing you "the Caspian Report of Asia" in a past video. In reality Caspian Report is to geopolitics as you are to technology. Where the both of you intersect is economics. You guys rock! 🤙👌
@@chromatron5230 I mean he does compile well-produced summaries. I also watch Johnny Harris since he really goes to the source, Good Times Bad Times for a more story-like timeline of events, and Armchair Historian who will almost definitely do a couple on the current Ukraine vs. Putin war once peace is brokered and the dust settles.
The mechanical side of lacing those patterns together is pretty incredible. Flying back and forth after the wafer has been out of the machine to etch away stuff and then back for another round 24/7. What do they use? Linear bearings with linear drive motors and magnetic encoders?
AFAIK, other than magnetic encoders (they use very high resolution optical encoders in semiconductor applications), yes they are. Tons of them, in fact.
??? Not sure what you mean here "lacing the patterns together"...Etching takes place in a either a wet process in acid etc. or a "dry" process in a vacuum chamber that is used to produce a reactive plasma to remove the films that are not masked by the resist from the litho print. Etch is a global process, all the wafer is etched at once. Making ICs is a layer by layer process, either adding materials to be subsequently patterned and etched, or global etches with no pattern where topography determines the remaining material etc. etc.
I am pretty sure they use air bearing stages. We were able to do 5 nm locations in 2010 with air bearing stages and interferometers to locate. This was for imaging for DNA sequencing.
@@redare7 A quick check shows ASML use magnetic bearings. Air bearings have been used previously in some older systems though, so you aren't that wrong.
No. HD single passes just overwrite part of the previous pass, leaving a small still readable strip. Multi-pattern photo-lithography writes several partial non-overlaping prints, composing a full "recording".
Shrink 👏 is 👏 always 👏 overlay. Multi patterning is a pain for eda but the advancement in overlay control is the key enabler of multiple patterning and shrinking gate pitch over all. I think your subscribers may want to see the actual gate pitch of each node, in nm! N5 is 51nm for example.
Fabulous content and video! I would like to nitpick on one point though. At time stamp 9:01, the video shows the coloring of the verities of a quadrangle. It claims that the number of distinct pattens stands at 18. It should be 12. The second row duplicates the first row.
Ive wondered, can we bring "FinFET" or "GAAFET" or the "VT-NW-Array-FET" to the 500-250nm range for hobbyists, and 45-28nm range for the startups? How much savings would there be? And then for AMD/Intel/nVidia it would probably be CNTFET in the 2050s
Thank you Asianometry. Having read and seen some other videos claiming to have achieved cutting edge manufacture of chips, comparing their information with yours makes it most clear that their claims are mere propaganda.
At 100eV an electron has the equivalent wavelength of 0.12nm. That allows very fine features to be patterned. Of course, scanning a whole wafer at that resolution would take days if not weeks, which is hardly what you need for mass production. The trick is: don't scan.
You would have to very accurately control and compensate for the surrounding magnetic fields or else the electrons would never hit the same place twice.
@@RingingResonance It really hasn't been optimised for a production process, or even a real device. When we ran e-beam write it was in cooperation with a university, who had the e-beam writer. It was used to generate structures smaller than could be printed by anything else at the time so that we could research advanced devices and issues that might occur/investigate solutions. Even then the size of the lines wasn't that small, we had printed lines around 70nm with production running 180nm, which was just about cutting edge for the industry then. From the 70nm we trimmed the lines down and etched straight poly and produced ~20nm etched features; we could have been better, but we were not running a hard masked poly process at that point, which would have made life a lot easier, we were really on the edge wrt resist left after the etch due to the trim. We were looking at just test structures and a few ring oscillators, not much active gate coverage at all and the write times were hours/wafer (for 8" wafers), for a full device, I think you would have been talking ~1 day/wafer. Let's say you wanted to do a 70nm device (not 70nm design rules, just with gates at 70 nm) you could just run e-beam for the gate layer, have larger gate landing areas for contacts. You would have shorter channel devices, let's assume you can sort the other issues involved with that channel length, then you end up with fast transistors, but the overall IC would be the same size, as you wouldn't have shrunk anything else. Would it be worth it? I really have no idea, but I suspect not, other than advanced investigation of small device issues to better develop the process as a whole. The thing is that a process once you start to hit 180nm and below starts to have lots of significant dependencies between upstream and downstream processes that all have to be optimised, which is not easy, and you tend to build on what you have learnt in each generation of process when you do the next one (at least you do if you have any sense) with some new modules being thrown in to make life really interesting and the engineering fun!
Thanks for your amazing video with remarkably clear explanation about the different lithography methods. I wonder if it is possible for you to make a video why no one talks about X-ray lithography? I mean, X-ray has a shorter wavelength than EUV, so I think it is logical to say that X-ray is more suitable when we go into even smaller nodes in the future. Has anyone tried it? What are the obstacles? Is it on the roadmap beyond High-NA EUV?
Ah, what they call "EUV" had a different designation when I was a physics student some decades ago -- we called that wavelength "soft X-rays..." So in one sense the industry has been doing X-ray lithography for a while now.
Yeah, EUV litho tools are really soft X-ray tools. The wavelength is 13.5nm. Also the optic are reflective, as is the reticle... I think there is a lot of learning to be had with EUV tools before we think about smaller wavelengths. TBH with the GAA transistors, I think the way forward is going to be with multiple layers of transistors and parallel processing rather than ever faster and smaller transistors, given most of the reasoning for smaller transistors is to increase transistor density. If you can build multiple layers of transistors, then a density increase can come from just adding another layer...(and of course dealing with the additional heat produced, you don't get something for nothing- This may get taken care of by diamond heat pipes, we'll see!)
@@erkinalp Yes of course it does, which was why I mentioned that there will likely have to be something like diamond films deposited between transistor layers to help bring the heat out of the core to heat dissipation structures. What this will be like I don't know, but diamond is a very good heat conductor...Current DLC films have thermal conductivities of up to ~3.5W/m.K which is better than Si (~150W/m.K), way off Cu (~400W/m.K), but you don't want any Cu around the transistors (bad things happen), and miles away from single crystal diamond (~2200W/m.K)! Improving the ordering of the DLC structure can increase the thermal conductivity, but there is a long way before it matches single crystal diamond.
1st Gen TSMC 7nm (aka no EUV) was a great node. Basic 7nm nodes can be done without EUV using multi-patterning JUST FINE! It's only at the 5nm class nodes where EUV becomes a practical necessity.
Great video. I never knew how Intel tried these quad-patterning methods or more to compete with EUV. In hindsight, they were crazy to brute force this with more patterning.
This is really very complicated Manufacturing process and it is a very hard and tedious process. And I would comment that for triple patterning or more, only the Asian workers could handle the tough environment.
X-rays are notoriously hard to reflect as they penetrate most things. Also I've been told that creating a photo-resist compound for x-ray lithography is pretty hard. Not because it's hard to find a material that crumbles when exposed to x-rays, but be cause it's hard to find a material that crumbles, but doesn't let x-rays through to destroy the previously made features.
@@andersjjensen thank for the answer!! :) But still I think reflecting them can’t be that difficult, because it’s something that happens in medical x-ray devices all the time. Why can’t they use heavy metal based photoresists?
@@CaptivaLP I'm not aware of medical equipment that reflects x-rays. It's generally "straight through". Even EUV is hard to reflect. The mirrors absorb quite a lot which causes throughput problems. DUV machines easily runs 300 wafers per hour whereas EUV machines are down to 150 at best. As for heavy metal based photoresist: I'm not a chemist, but I know that photo resist either needs to "crumble" or "cure", when exposed to the light source, depending on whether they're doing positive or negative reticles. Just applying a layer of, say, mercury, is not going to accomplish any of those. It's just going to block some of the x-rays. But if a chemical compound containing heavy metals can be found there's still a lot of other considerations, like how to dissolve the cured parts (or the crumbled parts) without dissolving chip features too, and how to reclaim the heavy metals so they don't end up in the sewer, and how to apply the photo resist in a perfectly even manner (These days that's done with vapour deposition. Don't know if it's a good or bad idea to turn heavy metals into vapour...).
Great video. When I use a word,” Humpty Dumpty said in rather a scornful tone, “it means just what I choose it to mean - neither more nor less.” “The question is,” said Alice, “whether you can make words mean so many different things.” “The question is,” said Humpty Dumpty, “which is to be master - - that’s all.”
I agree that regulating the nm names is sill, but i still consider thins to be simply false advertisement. You are saying the transistor is 7 nm, when in reality it has 14 nm gate.
How do you carry out your researches when preparing for a video? Curious to learn your strategy and methodology for finding leads and organizing information.
The best viewing date for this video should be one year from now. After experiencing commercial sanctions, Huawei still used DUV to make the 7nm chip Kirin 9000s, which has been used in the latest generation of Mate60Pro. Although there are evaluation videos showing that its energy consumption performance is even worse than Qualcomm Snapdragon 888, it is forced to Commercial sanctions are the only way out. Rather, I am surprised that they have actually achieved mass production of DUV7nm.This video is like a prophet😆
I once saw an image comparing the mask counts of a theoretical 5nm node without EUV to the N5 we got. Would that node be possible? Would something like self aligned octuple patterning be possible?
Lots of things are possible...but whether it is feasible to use for a production process is another matter. I etched 20nm gates on straight polysilicon from printed features @~70-75nm to look at various things that we would have to understand as the process nodes advanced. This was on planar transistors and was back in the mid 90's. We had functional 20nm transistors and we learnt lots of stuff that was very useful for process development of larger transistors, but no way was this a process that could be used to make an IC.
I want to meet those scientist, engineers and researchers were behind this marvelous technology. I strongly believe even after watching this video 100th of times, i couldn't totally understand the whole concepts. Nonetheless great video.
Feels like quite soon, we will plateau the performance, or at least we will slow down the increase in performance. Will be interesting then how that will affect the power consumption, when the compute power still increases.
Price and size, maybe(?) I mean, TRUMPF laser for EUV is around 40kW, while the largest synchrotron (by power) was PETRA II in Germany, with 12 GeV, which is roughly equivalent to 5.34058829*10^-16 kWh, and that facility was 2,4 km in circumference. Even France's 2020 ESRF is 6 GeV and still takes 800+ m in circumference.
Because everything has to work together - you need masks that can be imaged with X-rays, you need optics that can image the X-rays from the mask, you need materials that will absorb the X-rays for use as a resist layer...Not got one of these? It doesn't work! Oh yes, and it has to be defect free and play nice with everything else in the fab!
@@Muonium1 Ok, so I could just say "they can". But it isn't true...They need to develop an appropriate synchrotron source to give them the Xrays, then they need to produce and test masks to see if they'll work and likewise redo the optics. And research/produce a new resist that will absorb harder X-rays I strongly suspect that for significantly different wavelengths, they'll have to have a different set of optics that are designed to the wavelength, as I believe the optics are multilayer Bragg reflectors...good for the design wavelength, useless for anything else (well maybe useful for λ/n fractional wavelengths). Look at how long it took them to get the current EUV working, though if memory serves me right they started of with trying to get CaF2 lenses to work at 157nm, but had birefringence probs.
Ok, why don't they just name nodes after the transistor density? Like pixels on a screen, I don't care how they achieve it, I just care about my screen resolution. That's the measure the they should have been using all along as that's what Moore was referring to. Or better, use some measure of information throughout from Shannon. The fundamental issue is the frequency of bit decisions per meter^2. All the rest of this seems to be whatever hacks are needed to achieve that.
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Stay safe, everyone
First
Came here to get some fps in games
Thanks bro, we need it these days
I wanna read it 10 times too!
I find the elk on your profile picture very endearing and cute!
Your channel goes so far above and beyond in detail compared to others. You kill it bro, thanks for what you do.
bump
He kills the spellings of words as well
Information supplied by insiders?
@@GewelReal that marks originality!!!
Agreed, this channel is legendary. So much insight on what the industry's doing, and still explained clearly (or as much as it can be on those topics)
Thanks for your work!
Fantastic video, love the extra humor sprinkled in!
omg you’re here
About time you've discovered this guy. Hes great
I larfed a couple of times.
You new here? Watch his videos about "DRAM", and you will get XD
@@rem9882 he did long ago he even gave a shout out in one video
I went to a candid talk by someone from Intel back in 2012 and she talked very clearly about the challenges of going into EUV and the impossibility of it with the kind of lasers you need to *actually* get that feature size. I was surprised to find out over the years to see these headlines claiming that companies hit 14nm, 10nm, etc., when I know from my chemistry background just how difficult it is to get that kind of half-width level.
I'm surprised how difficult it is to learn the truth about what they're actually doing on the etching level without an explanation like this. Thank you for shaking me out of the stupor of years of marketing to see the truth that chip designers have been "cheating the barrier" to keep up with feature density growth.
This also explains why yields for everything, from PS5s to the M1s, are so terrible these days...
Aren't those(M1 and PS5) made with EUV now and so should have fine yeilds?
@@graficeb3484 EUV reduces the layers required vs. DUV-only lithography, so theoretically, EUV is easier. Playstation V's SoC (TSMC 7nm - N7p or N7+) is sizable 308-square mm die. Apple's M1 is on TSMC N5, which has better yields vs. N7.
It takes a while to perfect the process node. Newer processes will have worse yields. Due to production issues, TSMC had to delay its N3 node, which was supposed to be ready by mid-2022 for Apple A16 Bionic for iPhone 14. Also, Samsung is facing delays to their 3nm GAA node. The shrinking nodes are getting harder and harder to launch on time for commercial production.
If the chip is smaller (less defects per square millimeter), the yields are better, which is why AMD's CCX dies are primarily cores and cache. It was rumored that AMD's Zen II CCX dies had 70% yield on TSMC's 7nm process when production started. With time, TSMC figures out how to reduce defects and implements the fixes. Allegedly right now, TSMC's 7nm class nodes have statistically perfect yields. TSMC has a reputation of being the fastest to improve yields versus Samsung.
To get where you need to be with non EUV lithography means that you have to use "tricks" to shrink down the linewidth. What this functionally means at the 10nm± sizing is that larger lines are printed over various films, these are then etched to give a line that is your starting point.
Next you use the fact that you can deposit very thin films very accurately to deposit a thin film over the line (#1) that you then etch to leave a spacer (#1) which is narrower than the line you can print.
You can then remove the original etched line material, but leave the spacer; you then use this spacer (#1) as the mask for etching another lower film to produce another line (#2), and repeat the spacer dep/etch/remove line(#2) process.
Finally you etch the last layer of material to produce you final desired lines.
This is "quad patterning" and it allow you to reduce the size of your lines, because you use the spacers as the mask for the etching, the size of these is not limited by optics. You also reduce the pitch of your lines (ie distance between lines) because you have the spacer on each side of the line you use to make the spacers, again this "gets round" the optical limits of UV print.
The downside of this is increased process complexity, restrictions in patterning, additional processes to "cut" lines as printing line ends increases issues. Multiple layers to be deposited/etched. This all adds up to process time, complexity, and defects, because more steps means more defects, and hence lower yield.
If you have EUV, you can do a print/etch without playing tricks which is so much faster....and saves defects.
look at this www.monolithic3d.com/blog/the-quad-patterning-era-begins for a visualisation of the above. Note: this is a simplified view...
@@worldtownfc If a die is smaller then yield is better for a given defect density as p(defect in die area) is lower. If defect density is lowered you have the same impact, but from the opposite direction. You can also increase yields if you have built in redundancy to the design, such that you can "replace" an area with a defect with the equivalent circuitry in another area - this makes the die bigger, but it can improve yield more than reduced # of die on the wafer & hence reduce costs.
If you make your die on optimised processes for each function, as AMD has done, then you increase die yield due to smaller areas - you can tolerate a defect density more than larger die. Also the variation across a die will be smaller, as it takes up less of the print field, which may improve die yield if timing skews are critical or bin splits. It also allows better matching between speeds/voltage requirements of the chiplets.
BTW, unless they have changed, TSMC do not give a monkey's about your yield (they sell you wafers that meet certain criteria, not yield), as long as they meet the defect density they say they will and the electrical results they say they will. If your device has sensitivities to the process it is usually up to you to sort out your design, not for TSMC to tweak the process.
it's funny to think about the time when they were underpromising and over delivering, back when they first broke from the convention of "process node" = "actual gate length". In 1997, intel's 250nm process had a gate length of 200nm. later on it got "worse" with a 135nm process that had an actual gate length of 70nm. Now it's swung the other way. their 10nm process has 18nm gate length. From an almost 2x buffer to an almost 2x deficit.
This was really well done, as an instructor, I especially appreciate his humbleness to attempt to explain things he doesn't fully understand, and to do it in a way that inspires curiosity without superimposing arrogance. The description of the fuzziness around node technology is especially useful in deciphering both the history and evolution of this very complex intersection of technologies.
That was a hell of a explanation man, I'm really happy that I've found your Channel. Keep up the exelent work.
Very informative yet understandable. A new gold standard for RUclips videos. Highly interesting to see some of what's going on in chip technology. I always wondered why current chip designs looked much neater than older designs. Now I know.
The big reason that Intel struggled so much with the N10 and N7 nodes was etch yields. Since they had to do the crazy multipatterning etch defects would creep in and yield plummeted. Their etch vendors had to advance their tech to achieve acceptable yields. Once they did they have been ramping production to meet the backlog of orders ever since. And yes I am in the industry so I know this to be true.
I used to work in a semicon mfg and assigned at backend- moulding and dtfs area. I was not not able to take a peek at frontline on how dies are dice and wire bonded.
Reading and viewing your vlog about process how the billion of transistors are made in a wafer and the technology involved in doing this really amaze me.
I love the research and pictures you put into this to explain it. I used to have occasional magazine articles with this type of info to read. Those aren't really around anymore. This is great quality.
With every view, you’re honest to God teaching one more additional industry professional an insane amount of information about the industry they’re actively in. You’re likely doing more for the industry than you think. 🥰
I didn't know anything about semiconductor technology until I found this channel. And you have tought me so much!!!
This episode is frying my brain a little. I'm still processing the info, after watching a few times 😁😁😁
This is one channel i love for the content, but also for the extremely brief patreon plug, blink and you'll miss it, and that suits me just fine!! He says what he needs to in order to make us aware, and nothing more.
Perfect, just perfect.
Being one who work in this field, I commend you on this video! Awesome job.... but you pronounced Calibre in a strange way.... I teach Calibre applications for a living, so I kinda got hung up on that.
Heh, glad I wasn't the only one that noticed that - calibre => "cal-ih-ber", like "caliber"
@@gorak9000 It's the British spelling of the same word.
Thanks!
I don't even own a computer but Iv watched just about all asianometrys videos his a very good teacher
I appreciate you staying consistent for your pronunciations of ARF and DRAM.
So many insights in a single video, love this channel
I am tired of hearing about "7 nanometer", too.
Keep up the good work!
Terrific video as usual. I always wondered why further immersion wasn’t considered, there are certainly higher n materials than those liquids predominantly used in immersion. Anyway it’s moot now since EUV saved the day.
All materials have to be compatible with the other materials that are being used within the process and not add extra complexity or have problems with purity etc...
lmao I work in Lithography. The terminology is absurd. It makes more sense when you realize the scope/scale of the fabs and how everything has to be organized, but yeah it's funny.
I guess you must have a PhD? what process are you involved in, if I may ask.
@@MarkWTK no PhD. I work in a handful of processes including EUV. Right now I work on the metrology side of lithography..
@@MarkWTK for clarity, I work with 1272 to 1278 process within intel.
@@CRneu get read for the CCP'S attack.
@@CRneu I lost my badge access from Intel for making such comments... But I got to do some really cool shit internationally, 3rd party. Anyways... be careful.
You are absolutely the best source on chip technology in RUclips. More like chipometry asianometry. Glad I found your channel long time ago.
Do a video about KLA TENCOR , the leaders in metrology
Can you update this video in light of the MATE 60 pro which most likely uses this older DUV based method?
Waiting too
The only company that was able to develop a so-called "7nm" node without EUV has been Intel (Previously called Intel "10nm", now called "Intel 7"). You might be tempted to think that this is a great achievement for Intel, however it's actually their biggest blunder. Intel's decision to attempt developing Intel 7 without EUV by heavily relying on aggressive multi-patterning was the main reason they fell behind TSMC by 5-6 years (They were previously 2-3 years ahead of TSMC but now they are 3 years behind).
I agree with you. Intel 10nm era is such a disaster for intel. 10nm nodes from intel will never get intel back to the leadership despite intel released 3 revision to this node (10nm+ with ice lake, 10SF with tiger lake, and intel 7 with alder lake). But i still admire their enermous hardwork to make it work.
You are correct that Intel messed up on the transition to EUV, they held the orders for the first tools, but gave them up (which were then picked up by TSMC). I'd say the real issue here isn't size, rather EUV makes it easier to do more complicated gate designs (think GAA). WRT Intel yield problems at 10nm, vs AMD, I think that AMD were very smart to move to the chiplet approach, this allowed for better yields on poorer defect densities + using appropriate processes for different chiplets. (They got to have their cake and eat it). Intel continued with monlithic chips, which yield lower because of area.
Hopefully Intel does have a big order in for EUV systems, they need it, even if they order more than initially seems required, they could back fill "larger node" fabs with streamlined process flow to make yields better and gain experience on EUV, together with priming them for smaller node transition, depends on rate of tool delivery vs orders and speed of new fab ramps.
Not sure who gave up the EUV order, maybe Otellini, maybe Kryzanic, I do believe that they missed out on the growth of the foundries - Intel was it a good position to use their older process nodes and fabs as foundaries, that would bring in extra revenue, but more importantly starve the other foundries of some income. They started on it, but very half heartedly, this also saw a major growth and transition of IC production east to Taiwan etc.
I am optimistic with Gelsinger at the helm. He is of the same cloth as Grove, Barrett and Moore, though probably more like Grove. I am hopeful that he will also grow a foundry business too.
One thing I would consider here is that because of the DUV hardships you mention, Intel has a huge pipeline of innovation outside of the litho process specifically to make sure the pluses always actually were pluses. Meaning that when the DUV choke point is gone, Intel has an astounding amount of R&D that will separate itself from the pack. When EUV tools essentially are barriers for entry, they also become the floor of achievement for each foundry. The other innovations will decide the winners at that point. Will be interesting to see how much of Intels R&D portfolio is awoken when EUV nodes are fully the norm.
@@thecraggrat Intel had pretty big blunders due to terrible leadership, they were way too focused on finances than on the RND side of the company. There was a massive layoff of smart people "brain drain" which caused the decline of intel. Gelsinger currently rehired those retired people, so it might get better.
@@jakejakedowntwo6613 Ask yourself where intel 7nm is? They don't even hype it anymore, b/c it's so far away from actual production. It's another 10nm failure. Inside sources have been saying this for a long time, too. Intel is slowly admitting it. Their latest xeon roadmap (which we all know every intel roadmap that goes out longer than 6 mo is a lie), show 7nm for end of 2024 LMAO. Expect the lies to continue till you get nearer and that slips even further.
Who watches 10 minutes of digestible lithography content without being a computer design nerd?
Tech enthusiasts. Someone who is interested in knowing more about the most advanced and magic device ever made by humans.
@@OgbondSandvol sounds like something a computer design nerd would say
Eurythmy (dance) teacher here. I haven't a clue what I need this lithography knowledge for, still watched it.
@Señor Taco I have a few ASML stocks, indeed.
Industrial Financial Engineer Here(Industrial engineering
) , I just love Tech.
Thanks very much. You’ve provided much needed clarity on a complex subject.
Jon, you cheeky fella, you had me cracking up a couple of times with your remarks, it makes this video all the more worthwhile to watch, aside from the info and insights you provide.
Amazing content, congratulations and thank you for the time spent to do it!
Man I cannot find the right words to express my gratitude and salute to you. This video, as well as many others in the channel, provides a remarkable lot of knowledge to us. You deserve much better attention in RUclips in my honest opinion.
Very good as always. The video finally explained to me why Intel struggled for so long with N10. Amazing technology that advances so quickly, albeit with some steps and ramps.
I had read that China has some new technology that bypasses the need for ELV but I have not seen any details.
that's because it doesn't exist
this video kind of talks about that, it is possible but not practical. However China can probably get away without EUV for a while for most applications. I bet ASML and others are trying to come up with solutions that don't incorporate US IP too as US already talks about putting DUV on the list.
@@wpgc2 DUV is so old now that it is neither here nor there...Nikon sold DUV scanners ~20+ years ago.
Entertaining and Informative, John (Jon?)! Enjoyable too... and the droll humor is just a plus
With how unbelievably complex and interesting computer science is, primary schools need to be doing a lot more than just teaching code. Code isn't for everyone. However, insight into how math and science is applied into engineering these vastly important chips seems fundamentally important going forward.
The single greatest channel. That youtube every had for us. This young man is amazing.
Embarrassed myself the way I just whinged when the vid ended. Too good my man, bravo
I saw a compelling presentation once called “28nm forever” basically it made the case that the most cost efficient cheapest chips to produce would be 28nm (or let’s stretch to 22?) for a long long time if not perhaps eternity.
Not only is 28nm cost effective in production. It is basically also the end of power and voltage scaling. After that there are more transistors per area, but the transistors use the same power, so the ocerall power per area inceeases.
@@_TeXoN_ I don’t think I agree with you there, otherwise the R5 5600X would not be 65W for it’s performance. I’m not calling you out, I suspect there was some real academia saying this but my gut tells me it can’t be true judging by efficiency gains (per unit of performance or per # of transistors) that we have seen empirically.
@@depth386 Just read about Dennard Scaling. It is the physical equivalent to Moore's Law, but failed around 2005.
Everything below 28nm is also not a real measurement, but marketing names.
@@_TeXoN_ Okay I will look into that, and I do agree that “#nm” has become BS, Der8auer showed a 9900K and some Ryzen 3000 ground down to expose to die under an electron microscope, they were almost the same despite “14+++ vs 7”.
However, I am left with one more good question. Could you please explain to me, how are they packing more and more transistors? Transistor counts for both GPUs and CPUs are still going up by large percentages comparing one generation to the next. RTX 4000 series graphics cards are rumored to have 3x the 3000 series for instance. A little bit might be die size (and the recent trend of upward creep in power consumption) but there is still much progress in how many transistors they’re etching.
@@_TeXoN_ by the way I just read the wikipedia article on Dennard scaling. It’s not super in depth but it did give me an “aha, so that’s why i noticed going from Pentium 4 2.6Ghz to only 3.06Ghz i7-950 was like.. wtf? There were IPC gains and multi core gains but still, I was used to specs going up like 80386 33Mhz Pentium 1 133 Mhz Pentium 2 350Mhz Pentium 3 1Ghz Pentium 4 2-3Ghz it was tripling even without IPC advancements in the good old days
Great as usual, always look forward to your work
love your sense of humour :)
many thanks
Really, great work! Very good explanation and working through complexities, and vagaries.
The best channel ever in RUclips to get yourself educated in semiconductor industry and anything related to high techs 🔥🔥👌.. insanely detailed information 🤯.. It's free MIT level courses🤩.. Never missed a video..always waiting for more.. Thanks for the the extremely good work 😚😚
Another absolutely fantastic video: You’re one of the few channels where I watch every video from start to finish, as soon as I see them :-)
Holy moley, though: *Hexa” patterning? That must have had yield ~~0 😮
I was confused in this video by the illustration of the “spacer” layer. I was expecting the etching to happen where the spacer layer *wasn’t”, but it instead seemed to occur where it was present. Did I misunderstand or was that a graphical typo?
Thanks as always for the fantastic content; I can’t imagine how you find time in the day just to research and read the source material, let alone record and edit the videos themselves! 🤯
Sorry for dubbing you "the Caspian Report of Asia" in a past video.
In reality Caspian Report is to geopolitics as you are to technology. Where the both of you intersect is economics. You guys rock! 🤙👌
Caspian report is actually pretty surface level if u go deep into it
Like the lack of nuance as was said in this video
@@chromatron5230 I mean he does compile well-produced summaries.
I also watch Johnny Harris since he really goes to the source, Good Times Bad Times for a more story-like timeline of events, and Armchair Historian who will almost definitely do a couple on the current Ukraine vs. Putin war once peace is brokered and the dust settles.
The mechanical side of lacing those patterns together is pretty incredible. Flying back and forth after the wafer has been out of the machine to etch away stuff and then back for another round 24/7. What do they use? Linear bearings with linear drive motors and magnetic encoders?
AFAIK, other than magnetic encoders (they use very high resolution optical encoders in semiconductor applications), yes they are. Tons of them, in fact.
??? Not sure what you mean here "lacing the patterns together"...Etching takes place in a either a wet process in acid etc. or a "dry" process in a vacuum chamber that is used to produce a reactive plasma to remove the films that are not masked by the resist from the litho print.
Etch is a global process, all the wafer is etched at once.
Making ICs is a layer by layer process, either adding materials to be subsequently patterned and etched, or global etches with no pattern where topography determines the remaining material etc. etc.
I am pretty sure they use air bearing stages. We were able to do 5 nm locations in 2010 with air bearing stages and interferometers to locate. This was for imaging for DNA sequencing.
@@redare7 A quick check shows ASML use magnetic bearings. Air bearings have been used previously in some older systems though, so you aren't that wrong.
0:11 Is it available with Amazon Prime for next day delivery ? Can the delivery people just drop it at my door ?
This is like listening to a male version of Mandy giving a lecture on chip manufacturing. (The Grim Adventures of Billy & Mandy)
Big thumbs up for the detailed explanation. Particularly relevant to the AMD versus Intel battle right now.
Is photo-lithography without EUV the equivalent of multiple shingle writes passes on hard disks plate to achieve higher pitch density?
No. HD single passes just overwrite part of the previous pass, leaving a small still readable strip.
Multi-pattern photo-lithography writes several partial non-overlaping prints, composing a full "recording".
STANDING OVATION! Absolutely stellar episode! And 10 thumbs up for the use of applicable meme material! :D
Shrink 👏 is 👏 always 👏 overlay. Multi patterning is a pain for eda but the advancement in overlay control is the key enabler of multiple patterning and shrinking gate pitch over all. I think your subscribers may want to see the actual gate pitch of each node, in nm! N5 is 51nm for example.
thank you for all your research as always.
Fabulous content and video!
I would like to nitpick on one point though. At time stamp 9:01, the video shows the coloring of the verities of a quadrangle. It claims that the number of distinct pattens stands at 18. It should be 12. The second row duplicates the first row.
Great video like all of them you produce. Cant wait to see the videos on the Tech startups
謝謝！
9:02 the second and first row are identical, but they should be different.
Ive wondered, can we bring "FinFET" or "GAAFET" or the "VT-NW-Array-FET" to the 500-250nm range for hobbyists, and 45-28nm range for the startups? How much savings would there be?
And then for AMD/Intel/nVidia it would probably be CNTFET in the 2050s
Thanks for another fascinating and informative video! Chip engineering is really one of the most amazing tech-fields today.
I believe there is a mistake at 3:13, you meant to say 30% smaller instead of 70% smaller.
What about nano impress and other alternative to uv lithography like electron etching?
Amazing content about semiconductors. Keep up the good work.
Excellent clip! Very well done.
"Seven inches is not the same in one place as it is in another." I must remember that, it sounds important ....
Jon, sorry to disturb you, but does the recent report of SMIC about being able to do 7nm change anything?
IMO it simply means that those who thought that China would be in trouble were wrong again...
@@germancarrasco2028 I would agree with you, if you understood the difference between DUV and EUV.
Thank you Asianometry. Having read and seen some other videos claiming to have achieved cutting edge manufacture of chips, comparing their information with yours makes it most clear that their claims are mere propaganda.
So what's the gate pitch now we've moved to EUV?
And have they ditched all the added complexity of all that lelele stuff?
Nice, Question kinda related... Is there a way to find Vector files of the litho masks? Not necessarily functional, like die shots but vector....?
At 100eV an electron has the equivalent wavelength of 0.12nm. That allows very fine features to be patterned. Of course, scanning a whole wafer at that resolution would take days if not weeks, which is hardly what you need for mass production. The trick is: don't scan.
You would have to very accurately control and compensate for the surrounding magnetic fields or else the electrons would never hit the same place twice.
Yeah, it's called direct write lithography, but it isn't really practical for production (well depending on what you are making).
@@thecraggrat SO it IS possible? I wonder what kind of chips have been made using that process. Probably something crazy.
@@RingingResonance It really hasn't been optimised for a production process, or even a real device. When we ran e-beam write it was in cooperation with a university, who had the e-beam writer. It was used to generate structures smaller than could be printed by anything else at the time so that we could research advanced devices and issues that might occur/investigate solutions. Even then the size of the lines wasn't that small, we had printed lines around 70nm with production running 180nm, which was just about cutting edge for the industry then.
From the 70nm we trimmed the lines down and etched straight poly and produced ~20nm etched features; we could have been better, but we were not running a hard masked poly process at that point, which would have made life a lot easier, we were really on the edge wrt resist left after the etch due to the trim.
We were looking at just test structures and a few ring oscillators, not much active gate coverage at all and the write times were hours/wafer (for 8" wafers), for a full device, I think you would have been talking ~1 day/wafer.
Let's say you wanted to do a 70nm device (not 70nm design rules, just with gates at 70 nm) you could just run e-beam for the gate layer, have larger gate landing areas for contacts.
You would have shorter channel devices, let's assume you can sort the other issues involved with that channel length, then you end up with fast transistors, but the overall IC would be the same size, as you wouldn't have shrunk anything else. Would it be worth it? I really have no idea, but I suspect not, other than advanced investigation of small device issues to better develop the process as a whole.
The thing is that a process once you start to hit 180nm and below starts to have lots of significant dependencies between upstream and downstream processes that all have to be optimised, which is not easy, and you tend to build on what you have learnt in each generation of process when you do the next one (at least you do if you have any sense) with some new modules being thrown in to make life really interesting and the engineering fun!
These vids really are excellent. As easy as reasonable to understand
It can be done but what is the yield
Thanks for your amazing video with remarkably clear explanation about the different lithography methods.
I wonder if it is possible for you to make a video why no one talks about X-ray lithography? I mean, X-ray has a shorter wavelength than EUV, so I think it is logical to say that X-ray is more suitable when we go into even smaller nodes in the future.
Has anyone tried it? What are the obstacles? Is it on the roadmap beyond High-NA EUV?
Ah, what they call "EUV" had a different designation when I was a physics student some decades ago -- we called that wavelength "soft X-rays..." So in one sense the industry has been doing X-ray lithography for a while now.
Yeah, EUV litho tools are really soft X-ray tools. The wavelength is 13.5nm.
Also the optic are reflective, as is the reticle...
I think there is a lot of learning to be had with EUV tools before we think about smaller wavelengths. TBH with the GAA transistors, I think the way forward is going to be with multiple layers of transistors and parallel processing rather than ever faster and smaller transistors, given most of the reasoning for smaller transistors is to increase transistor density. If you can build multiple layers of transistors, then a density increase can come from just adding another layer...(and of course dealing with the additional heat produced, you don't get something for nothing- This may get taken care of by diamond heat pipes, we'll see!)
@@thecraggrat With more stacking comes more heat...
@@erkinalp Yes of course it does, which was why I mentioned that there will likely have to be something like diamond films deposited between transistor layers to help bring the heat out of the core to heat dissipation structures. What this will be like I don't know, but diamond is a very good heat conductor...Current DLC films have thermal conductivities of up to ~3.5W/m.K which is better than Si (~150W/m.K), way off Cu (~400W/m.K), but you don't want any Cu around the transistors (bad things happen), and miles away from single crystal diamond (~2200W/m.K)! Improving the ordering of the DLC structure can increase the thermal conductivity, but there is a long way before it matches single crystal diamond.
@11:13 What, no pronunciation of SAQP? Very disappointing... :)
What about EUV lithography via steady state microbunching using sychrontrons to produce EUV photons? Could you please make a video on that...
Really scares for general production are not EUV based chips but those for cars and other useage from 30 to 14nm.
1st Gen TSMC 7nm (aka no EUV) was a great node. Basic 7nm nodes can be done without EUV using multi-patterning JUST FINE! It's only at the 5nm class nodes where EUV becomes a practical necessity.
Great video. I never knew how Intel tried these quad-patterning methods or more to compete with EUV. In hindsight, they were crazy to brute force this with more patterning.
Amazing as usual. High quality content of the most high tech technology.
This is really very complicated Manufacturing process and it is a very hard and tedious process. And I would comment that for triple patterning or more, only the Asian workers could handle the tough environment.
That's for the details. It must have been taxing.
Is changing the material from Si to Ge possible? Is there enough advantage for doing that? I know how to make high quality Ge on Si.
Hey i have a serious question. Why isn’t there something as x-ray lithography. And why isn’t it being used??!
X-rays are notoriously hard to reflect as they penetrate most things. Also I've been told that creating a photo-resist compound for x-ray lithography is pretty hard. Not because it's hard to find a material that crumbles when exposed to x-rays, but be cause it's hard to find a material that crumbles, but doesn't let x-rays through to destroy the previously made features.
@@andersjjensen thank for the answer!! :)
But still I think reflecting them can’t be that difficult, because it’s something that happens in medical x-ray devices all the time. Why can’t they use heavy metal based photoresists?
@@CaptivaLP I'm not aware of medical equipment that reflects x-rays. It's generally "straight through". Even EUV is hard to reflect. The mirrors absorb quite a lot which causes throughput problems. DUV machines easily runs 300 wafers per hour whereas EUV machines are down to 150 at best.
As for heavy metal based photoresist: I'm not a chemist, but I know that photo resist either needs to "crumble" or "cure", when exposed to the light source, depending on whether they're doing positive or negative reticles. Just applying a layer of, say, mercury, is not going to accomplish any of those. It's just going to block some of the x-rays. But if a chemical compound containing heavy metals can be found there's still a lot of other considerations, like how to dissolve the cured parts (or the crumbled parts) without dissolving chip features too, and how to reclaim the heavy metals so they don't end up in the sewer, and how to apply the photo resist in a perfectly even manner (These days that's done with vapour deposition. Don't know if it's a good or bad idea to turn heavy metals into vapour...).
Great video.
When I use a word,” Humpty Dumpty said in rather a scornful tone, “it means just what I choose it to mean - neither more nor less.”
“The question is,” said Alice, “whether you can make words mean so many different things.”
“The question is,” said Humpty Dumpty, “which is to be master - - that’s all.”
I agree that regulating the nm names is sill, but i still consider thins to be simply false advertisement. You are saying the transistor is 7 nm, when in reality it has 14 nm gate.
How do you carry out your researches when preparing for a video? Curious to learn your strategy and methodology for finding leads and organizing information.
Check out the Compounding Curiosity audio podcast, in one episode he talks about his research process.
Your tech memes are on point.
10 seconds into the video. I wonder, didn't tsmc make their first gen n7 process with duv?
The best viewing date for this video should be one year from now. After experiencing commercial sanctions, Huawei still used DUV to make the 7nm chip Kirin 9000s, which has been used in the latest generation of Mate60Pro. Although there are evaluation videos showing that its energy consumption performance is even worse than Qualcomm Snapdragon 888, it is forced to Commercial sanctions are the only way out. Rather, I am surprised that they have actually achieved mass production of DUV7nm.This video is like a prophet😆
Cost more to make (as n+2) lesser output in batch but the margin is high enough for huawei.😂
Seems SMIC managed to do it. All good … love 🇨🇳
I once saw an image comparing the mask counts of a theoretical 5nm node without EUV to the N5 we got. Would that node be possible? Would something like self aligned octuple patterning be possible?
Lots of things are possible...but whether it is feasible to use for a production process is another matter.
I etched 20nm gates on straight polysilicon from printed features @~70-75nm to look at various things that we would have to understand as the process nodes advanced. This was on planar transistors and was back in the mid 90's. We had functional 20nm transistors and we learnt lots of stuff that was very useful for process development of larger transistors, but no way was this a process that could be used to make an IC.
7nm without euv will be great boom for low end laptop in the future
this video is incredibly interesting and formative
It's funny I was investigating the exact same thing before you made that video.
I wonder when 1nm will be achieved.
NXT double exposure can make 7nm chip ?
dishonest marketing is just redundant
I want to meet those scientist, engineers and researchers were behind this marvelous technology. I strongly believe even after watching this video 100th of times, i couldn't totally understand the whole concepts. Nonetheless great video.
Dr.. ambedkar can do reservation for making euv machine 😅
Feels like quite soon, we will plateau the performance, or at least we will slow down the increase in performance. Will be interesting then how that will affect the power consumption, when the compute power still increases.
Learning so much from this channel but this stuff is way over my head. LOL
Isn't intels 10nm process equivalent to other's 7nm, which has been rebranded as Intel 7 not use EUV?
I knew this was complex, but holy crap I didn't think it would get this complex.
why can't they just use sychrotron light to produce arbitrary wavelengths down to x-rays and at super high intensities?
Price and size, maybe(?) I mean, TRUMPF laser for EUV is around 40kW, while the largest synchrotron (by power) was PETRA II in Germany, with 12 GeV, which is roughly equivalent to 5.34058829*10^-16 kWh, and that facility was 2,4 km in circumference. Even France's 2020 ESRF is 6 GeV and still takes 800+ m in circumference.
Because everything has to work together - you need masks that can be imaged with X-rays, you need optics that can image the X-rays from the mask, you need materials that will absorb the X-rays for use as a resist layer...Not got one of these? It doesn't work! Oh yes, and it has to be defect free and play nice with everything else in the fab!
@@thecraggrat all of that was just as true in the case of tin plasma EUV
@@Muonium1 Ok, so I could just say "they can".
But it isn't true...They need to develop an appropriate synchrotron source to give them the Xrays, then they need to produce and test masks to see if they'll work and likewise redo the optics. And research/produce a new resist that will absorb harder X-rays
I strongly suspect that for significantly different wavelengths, they'll have to have a different set of optics that are designed to the wavelength, as I believe the optics are multilayer Bragg reflectors...good for the design wavelength, useless for anything else (well maybe useful for λ/n fractional wavelengths).
Look at how long it took them to get the current EUV working, though if memory serves me right they started of with trying to get CaF2 lenses to work at 157nm, but had birefringence probs.
Ok, why don't they just name nodes after the transistor density? Like pixels on a screen, I don't care how they achieve it, I just care about my screen resolution. That's the measure the they should have been using all along as that's what Moore was referring to. Or better, use some measure of information throughout from Shannon. The fundamental issue is the frequency of bit decisions per meter^2.
All the rest of this seems to be whatever hacks are needed to achieve that.
To get a perspective on how small 7/5nm is Point a laser at the moon on an astronauts thumb the dot is 7nm .
So what is EUV? Does it make lasers smaller?