The History of the Semiconductor Photomask
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- Опубликовано: 28 авг 2024
- As a fundamental part of the lithography puzzle, the photomask has a fascinating history that goes all the way back to the very beginning.
So in this video, we are going to look at this essential piece of the semiconductor manufacturing process from rubylith to EUV: The photomask.
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So nostalgic. My first IC design, a silicon bipolar (gold doped) counter, using ruby in 1960s. Errors in ruby masks were search for for hours. Sign off was required by three engineers, test, production and design. My first design, just out of college, worked and beat the competition. They gave me a 30% raise! Each week I cashed my paycheck and carried the money in my pocket for a few days.....My last design was in the 2020s, an extremely low phase noise VCO in CMOS. Working in semiconductors was a fun trip. I miss the challenges and people.
You can always go Sam Zeloof :P
But why did you stop designing them?
@@alexa.davronov1537if he quit after 2020, it's because he retired...after approximately 60 years in the biz.
you would be an interesting person to have dinner with, the stories you could tell!
Amazing comment. Enjoy your retirement. You deserve it!
My dad used to work in R&D for this stuff back in the 70's while developing a gate library for a 5 micron process. Defects where high at first, so a lot of stuff was discarded. My dad brought home a collection of, er, "souvenirs". No Rubylith, of course, but I have a bunch of 10x and 100x Mylar reductions, and several original photomasks, some of which still have their pellicle intact (which is impressive, seeing how thin and fragile these protective layers are). One of my favorite things to do when I was a kid was look at this stuff and tons of reject wafers under a microscope.
I didn't appreciate how privileged I was to have access to this kind of technology and use real Calma and Apollo systems at the GTE Student Workshop. At the time, I kinda figured this is what everyone's dad did at work. 8)
That's awesome. I wish there was a museum which had images of the designs of these chips. We may buy the CPU, but we will never know the beautiful designs that went into designing these processors.
I also did Mylar reductions in my student days of 1985, to make a 4 bit shift register in 100 micron scale to prove I understood the process, using an ancient 1970’s machine, ven turning on the taps for Boride and Phosphorus gas. I then did a 3 micron VLSI chip design using Bell. It came back 5 months later as 2.5 micron, as the 3 micron process became obsolete in the gap.
Yes I used to make rubylith masks for thick film printing and that was painful enough let alone trying to cut a chip design. It was quite satisfying when done but stressful until the last strip had been removed without tearing.
did you use tapes to secure the film?
@@Theoryofcatsndogs To be honest it was such a long time ago Im not absolutly sure but Im pretty sure we did. I was cutting against A1 graph paper and that was stuck with tape to a light board so it would seem sensible have taped the rubylith but I know it was sensitive so it would have been masking tape not packing tape. The only reason for my hesitation is we did have a vacuum table too but I dont recall using that for this
oh shit, didnt think about tearing ..the delicate balance of piercing just enough to peel and not enough to tear
This has got to be the best video on chip manufacturing. Every other video glosses over the creation of the photomasks as if it's trivial, but it's the key to the process.
I still don't understand how they produce a stencil with billions of transistors on it
Thanks! You have a gift for making the potentially mundane ....entertaining. More of these would be welcome 😊
Zwischennegativ (German) is a compound word, consisting of:
1. Zwischen (en: in-between).
2. Negative (en: negative).
- which clearly describes its purpose being an intermediate scale negative.
Pronounced "tswissionnehgahteev".
As always wonderful video.142x142 without any defect and that after passing multiple foup door openers, handling robots, heating chambers, ald units, etc is a feat in and of itself. There is always a particle, no matter which size, waiting around the corner to sneak in and ruin your day. You should consider making a video about the crazy tech behind ISO 1 cleanrooms and what it takes to keep them in check.
3:44 This has brought memories back of working on primitive GCA resist and developer track systems back in the 1980s. They were programmed via paper tape, and would literally blow the 4" wafers along a track from cassette to spinner to apply resist, then bake and on to another cassette. If a wafer covered in resist broke in the spinner it was a real mess to clean up. We didn't have a GCA stepper though, the wafers would go to a Perkin Elmer Micralign or a Canon mask aligner, or later steppers.
In the early days of the chip shortage, I was confused because I understood only that the lithography process was very similar to shirt screen printing. But your other videos have helped me to learn how much more complicated it is to make modern chips.
What chip shortage? The current? There have been numerous for the last 50 years.
Electrostatic chucks (esc’s) are very common in etch, implant, ash and pvd steps. Mechanical clamps went away during the 200mm years.
When I started the mask making and inspection tools were still in the fab, but retired. I’ve run perkin elmer aligners up to DUV step and scan, with contact and proximity aligners and a bit with EUV along the way.
Pellicles are important to repeatability, but when an expedite lot came along I personally went to shipping and repossessed a needed mask, ripped off the damaged pellicle and ran the product. Even a 50% yield loss was preferable to missing a shipping deadline. The focus shift was within tolerance for the layer.
We remember resist overflow at the back of the wafer that caused e-clamping issue at our implanter with e- clamp type of chuck
So masks with damaged pellicle were sent for repair?
Did you know that initially ASML and Intel did not want a pellicle on the EUV mask? Back in 2009 or thereabouts, the EUV light source did not have enough power and therefore the stakeholders wanted to eliminate anything that would absorb the EUV light. The pellicle materials available at the time would absorb the EUV energy. The entire EUV litho chamber (wafer and reticle stage) has to be a vacuum so that the air won't absorb the EUV energy. To introduce the EUV reticle into the chamber, the reticle pass-through had to be pumped down to a vacuum, and therefore the reticle pod had to be all metal to keep the pumping time as short as possible. No pellicle, no polymer contact points on the reticle pod meant that the hard metal contacts gauged the reticle glass, causing particles on the non-pellicle EUV mask. So ASML decided to allow super tiny polymer contact points in the reticle pod to prevent such gauging. And eventually a very low absorption pellicle was developed and more powerful EUV light sources were realized. It was a lot of fun working on this stuff!
Oh rad video. I work in CD-SEM right now, mostly with Hitachi tools, so this video is very on point for me. I've also worked directly with reticles/masks in relation to Nikon and ASML stepper tools and even opened up the reticle pods for inspection, so again this hits pretty close for me. I often recommend your videos to coworkers. Another great video!
15:34 the print area in use is 142x136. Some defects are acceptable in areas that can be obscured by the pattern, i.e. hidden under the carpet.
While rubylith has been replaced with digital tools in screen printing, the photolithography process is mostly still there. Printers use exposure units to burn an image into a screen impregnated with emulsion. Wash out the uncured emulsion and force ink through the screen to make an image.
What time is it? I don't know. Do you? No. Nobody does. Something might. Not possible to discuss a nothing. Not sure. No way of knowing. Hair? Yes. For now. No hair equals hair. Yes? Yes. No. Hair? Hair today not sure when. Transistors are smaller than hair. Sometimes? Two times. Three. Hair.
Oh if you put the work into a video about the Cambrian explosion like you do with all your others I’d watch it in a heartbeat ❤
Pangeanometry
@@chefnyc haha love it!
Fun playing with slabs of *_Burgess Shale..._*
I appreciate your videos so much!
Having studied electrical engineering in the early and mid 1980's and upon starting my career as a test engineer (designing a building tests for a process control product line, plenty of analog and digital) it seemed the need for EE's was going overseas. Hence, I moved into supermini computers and learned the architecture of such things as ECL processors with such things as "burst pipeline architecture". Eventually I moved into Fintech, but kept my hand in the EE side, being able to visualize how virtualization typically offiscates the sources of nonperformant causes (because they happen on the actual/physical hardware).
I sure appreciate catching up and learning a bit about this end of the technology stack.
No need to flex so hard. Make a separate story time comment! I do want to hear more
IC masking and screen printing: Well, I think more accurate to say that these techniques were well known from the manufacture of printed circuit boards, which were in full swing at the time of the first ICs, and from there you get back to printing, both screen printing and lithography. Also, resists were in use before ICs, used to perform etching on metal, rock and other surfaces, which is very much a thing today. In fact, etching glass with acid, still done today, is almost a direct line to ICs, since silicon dioxide is basically glass.
07:36 Seeing this GCA stepper at the Cornell Nanoscale Facility (CNF) brings back fond memories of working with the 5x g-line and the AutoStep 200 (i-line) back in the day! I remember when they later added a used ASML DUV as well. CNF remains an excellent place for hands-on training in semiconductor processing!
Hooray, we got the 5k upvotes, so looking forward to the follow-up on measuring and correcting defects.
Nothing scratches my nerdy itch like Asianometry's YT channel.
We used stereolithography to print 3D models of patient's heads using MRI scans in the 1980's and 90's =)
Was a super cool tech at the time
It’s really amazing that making microchips is basically just figuring out how to make really really tiny mono color photos.
You know we want that defect detection video 💪
Nice!!! I liked the early history part!
But then there was a big jump, skipping over: migration from 5x to 4x masks, alternating phase shift masks and attenuated phase shifting masks before you got to the masks for EUV.
Did you know that there have been investigations into maskless lithography? And direct write ebeam lithography?
I remember that, E-beam litho. It was way too slow, as electrons repel when you have many of them together.
I like this new school teacher approach of asking a question requiring thought, then the patreonewsletter, then the time is up. John's assurance that he knows more than the kids in class steps up every week (as their minds get blown).
Would you be able to talk about the company Lasertech in future videos? They seem to be dominant in photomask defect inspection equipment. Thanks a lot for all the great informative videos!
Stamp of approval (as all of your vids get) from a lil litho engineer me
Sir , your videos are exceptional, thank you for being a wonderful decent human and putting so much hard work into helping others gain knowledge
Another instructive video. I always learn a lot. 👍
For those who work on MEMS and microfluidics contact aligners are still used a lot, because it’s easier to design custom (foil) masks. They often only use our ASML stepper to expose a zero layer with all their alignment markers.
I grew up in a sign shop my parents owned in the 90's and we used Rubylith to make silk screens, I had no idea it was used for semiconductors.
One man’s tshirt is another company’s gpu design. 🤣
Might come full circle once people start integrating electronics into clothing.
@@brodriguez11000 they are now...the market is called wearables. :)
I remember the rubylith mask making from my graduate school days in a microelectronics and VLSI research laboratory in the 80's. Things have really moved quite a bit since those early days. Things have become so increasingly 'hi-tech' that setting up a plant can cost up to double digit billions of dollars.
Great content, as always.
Maybe you could do a follow-up video with leading edge mask writers (the dawn of VSB and birth of Multibeam mask writers), Mask inspections (CD measurements, Registration measurements, Defect inspection and Mask repair).
That's an amazing introduction to the field, I'm waiting for the follow-up !
A series of chip history would be great 🤙
I used to make the PCB traces up with roles of tape and roles of adhesive track pads.
Thanks for the many fabrication videos that you've produced. I loved the time I worked in the industry and you bring explanations that I didn't know even after 20 years.
"I do love how early semiconductor people were just borrowing here-and-there from all sorts of different industries." Or as Werner Herzog said: "We are not garbage collectors. We are filmmakers. We are thieves. We get away with loot from the most beautiful or the most scary."
Maybe time to rename the channel to “Semiconductors and other stuff”. I get super excited when one of these videos come out. Nothing wrong with how different countries messed up land reform or high tech industries..
Thks & I kinda followed the cool domain jargon but still half was over-my-head.
Request you do a chip-stuff for dummies like-me playlist w/o all the cool domain jargon.
Great video! Thanks for the effort you put in for making such high quality videos
Another home run! Absolutely love your videos.
day 2 of asking Asianometry to cover nanoimprint, complementary electrom beam litography or other alternatives to EUV
Fun fact, while researching the topic i found that inmersion litography can be done with solids, so duv could be extended even more than it already has
None of those are alternatives to EUV. They can be used to make chips both cheaper and faster than EUV. But if you require the feature size of EUV lithography there are no alternatives.
@@andersjjensen nanoimprint litography and electrons beams can be used for smaller features, specially the latter. However they are untested for high end processes
Looking forward to the follow up video on EUV Defectivity!
6:19 I stopped to read what the (stock footage) printing plate said: The text is truncated in all directions. However, it appears to be a summary of someone's biography who lived approximately 100 years ago visited school, joined the Army during the First World War, survived and completed school afterwards. Apparently, this person grew up near Trier and later moved to Essen.
Another excellent episode, support and growth of this channel is very logical and inevitable! Keep on doing great work!👏
a chuck in industry and machining is a tool used to hold other tools like drill bits and end mills or the work itself like on a lathe, so an electrostatic chuck is just a work holding tool that holds via electrostatics rather than physical or magnetic clamping that is used in the macro scale.
It’s funny how screen printing is still an important step in the semiconductor industry with the use of stencils for printing solder paste onto bare PCBs.
14:50 chromium nitride (a tough, wear resistant compound, like many other metal nitirdes) is confused with chromium nitrate (a meh water soluble salt)
Sir, thank you for making those videos so interesting and accessible.
Nowadays the cutting-edge stuff is nearing 4 NANOmetre-sized elements. That's 4/1000ths of a micrometre - And they keep getting smaller. We're already experiencing issues with electrons wandering through a switched-off transistor thanks to Quantum Tunneling, but somehow that is worked around and size keeps shrinking. Before too long we could be working with elements measured by individual atoms.
If you want to make a video about the Cambrian explosion, I for one would gladly watch it.
10:47 i think that image more accurately represents the Ediacaran period rather than the Cambrian.
Or pre-Cambrian if you want to call it that
Great !
I remember years ago reading exactly the same extract from the book about Commodore and always wanted to see images of manually drawn 500x mask precursors but was never able to find the appropriate keywords to google it successfully.
Thank you !
Maaaeeehhsks? At 13:00. Was that on purpose? Awesome history lesson. I worked somewhat in the printing industry, avid photography noob, and am getting into printed circuit boards now. Love your content.
Yes! Been waiting for this one for a long time
You do a fantastic job in your explanations. Glad I found your channel last year!
Please do make a video on the Cambrian explosion. I know it's not really the genre you do but honestly it's a very interesting time on earth.
Thanks for another great video! (Cambrian explosion - yes please!)
Rubylith!! I mentioned it at work the other day and except one "mature" engineer, nobody new what it was. 😆
While at uni, I caught the very end of the rubylith age. By that time, it was only used for thin film hybrid integrated circuits, to help create the conductive pattern on glass or ceramic (I think... We used glass). By the time I started work, I never heard rubylith mentioned.
I liked the colour though. Very ruby! 😀
My first experience in chip making was in the mid to late 70's when I worked for (Milgo->ICC-> Racal-Milgo)'s and their development of the 24LSI and subsequently the 9600 LSI modems. The custom chip(s) in these were fabricated using Rubylith masks.
Amazingly interesting. I do "human-size" board design, and yet I know almost nothing about high precision lithography. Love videos like these.
@13:29 the print area is 142x142 the total area is 152x152mm, AKA "6" inch mask, 1/4 inch thick.
As far as I know, at 1x the largest image field that can be exposed on a scanner is 26 x 33 mm (rectangular).
@@tommy2cents492 That's after 4x reduction in scanner. 26x33 mm *4 in all dimensions = 132 * 104 mm for the main device layout on the photomask. The remaining area can be covered with Labels, test patterns, markers, barcodes, etc.
Gosh I love this channel
14:19 If there's more than 2 zeroes it's best to go to scientific notation or use some other well-understood shorthand (like ppb)
In 1970, I took an engineering class in integrated circuits, and we had a tiny IC lab. Each team had an IC project, and my lab partner and I started to design and build a two transistor flip-flop. We used rubylith to make the masks. As I recall, our rubylith material was clear palstic sheeting with a layer of red film on top. There was nothing photographic about it. The machine to cut the pattern was as you describe, and one interesting detail was that the cutter had to be manually aligned to the direction of the cut (up/down left/right). If you had the cutter set incorrectly, you would either ruin the rubylith pattern or break the cutter. Anyway, we did'n't finish the project, but we made all the masks and started a few diffusions. It was a great course, and I still have a few of the little masks (about 1.5 inches square).
I want to see the video on defects and their corrections next for sure!
Now I want to see the Cambrian Explosion video you'd make
You should do a video on the Cambrian Explosion.
Please do more!
Great video thanks
Please make a video about the Cambrian explosion!
Hi Asian, please tell Onometry she got it wrong about the 6 PPM @14:10 , as PPM always refers to the full base unit, hence 6 PPM ( of a _meter_ ) is : 0.000006 mm (six millionths of a millimeter = 6 micrometres = 6 µm). That is odd, as PPM is very rarely used for lengths.
Thanks!
Yooooo
this is posolutely s-tier content
Excellent video!
I’ve done Rubylith! Wish I had the ability to just send data and receive a mask back then. No, all the reduction steps and chemical steps…
I'm halfway through Chris Miller's book Chip War at the EUV chapter. In light of the recent Chip Act and the executive orders regarding the sale of chips and chip making equipment to China by the Biden White House, how about a video explaining how these recent developments effect the chip industry as a whole and China in particular?
Or how ASML or TSMC are investing in US. I see bunch of US job openings lately.
Sadly comment moderation would not allow me to honestly write my feelings towards these politicians and the sinophobia they incite.
Awesome, thank you for making this!
What about the 1979 Fujitsu X-Ray Chlorine etching? The X-Ray is tuned to the energy needed to disassociate the chlorine molecule. Thus where the mask allows the laser to pass, the chlorine ions etch the substrate, eliminating the resist. Coupled with the X-ray mirrors, the X-ray laser intensity can be high.
It's even better to think about screen printing techniques being used to create chip tech that ultimately killed most paper-based media that gave birth to it. Sounds like a perfect Greek tragedy adaptation to me.
Incredibly interesting video as always!
Please make a video about Cambrian explosion!
Amazing video, this has to be one of the top videos to ever be made I. This subject. Bar none. Great work. I’ve been waiting for this video for a long time from you.
Resist coating that has not been stripped well is the "enemy" of Implant as too much outgassing is experience in the early days of wafer manufacturing. We will just see the chamber and the surrounding area as full of resists by products that cause potential wafer scrappage due to particle during implant. Wafer patterns are scratched in a batch processing type of implant.
IC masking is more dark magic than high-tech machinery.
Thank you for this video...
Great job! Thank you!
Try "Tsvishen-Negateef" that should sound about right.
It just means intermed- or in-between negative.
@asianometry Please make a video about the Cambrian explosion
Second the motion.
Nice videos, but can you do anything concrete about the chip shortage? You seem to benefit from so much knowledge..clearly you are ahead of us! :)
'zwischennegative' is pronounced with the German 'zwischen' which is English 'between' -- it just means 'intermediate negative'.
It was not specifically mentioned if TSMC also makes EUV masks? Or "develops" them at least (to use a photo analogy), as I'm sure they're not trying to make the reticle mirrors from scratch.
Do you mean printing the EUV masks, or manufacturing the EUV masks? As mentioned in video, TSMC has their own maskshop for printing of the masks. From manufacturing point, there are few players on the field, but one company owns almost entire market of EUV masks (and I think the company was not mentioned in this video).
@@michaljurkovic I meant the printing part.
2:37 is an intriguing connection.
*nodding along like I understand more than 25% of what he's talking about*
Either way I love the videos
Love your videos so much!!!
Have you considered doing a video on the Iranian or Turkish semiconductor industry?
No wonder TSMC engineers get paid big bucks... I mean at its core it's basically silk screen printing that anyone can do in their garage but it's so precise.
you got that right.
At Intel in the 70's we always put 4 "test coupons" on the edges of each wafer and during the process we tested their function with probes and if they all didn't work we would shitcan the wafer to keep from packaging crap circuits ... wonder if they still have to do that today?
I don't think so. Wafers need to be extremely uniform throughout all the processing steps. Having dedicated coupons would break that uniformity and may lead to performance issues in adjacent dies.
The amount of wafer metrology has exploded over the last decades to monitor all processing steps. I think that information is used to predict final yield. Being a 'yield engineer' is not easy...
So the ICs were not tested before bonding? But when already placed in a DIL package?
@@herrbonk3635 No tested even before dicing up the wafer using super find probes adjusted for the coupon circuit.
@@tpcdude Yes, that's what you said. But I meant the other normal ICs. If they were tested before bonding and packaging what would "packaging crap" mean?
What is done is putting test circuitry, test points, etc. in the area between the dice. Once a wafer has been fully fabricated all the dice on the wafer are tested and any defective ones are marked. The test circuitry ends up being destroyed when the wafer is sliced.
Here's how you pronounce the German word "Zwischennegativ":
*Z* - Like the ts is *Ts*-unami
*w* - Like the V in *V*-ogue
*i* - Like the E in *E*-ar
The German word "Zwischennegativ" is a compount word of "zwischen", which meaning between or intermediate) and "negativ", which just means "negative".
Cvisshen negative - roughly translates to in-between negative 02:55
Quite funny pronunciation of "Zwischennegativ" xD
Greetings from Germany!