This is best channel for the people who are started their carrier in VLSI. Amazing content that you are providing, really appreciable your efforts and giving information freely to the people. If possible, please try to upload all the videos which are related these topics. Thank you madam 😘
Great content. Thank you. I have a few doubts though. 1. Why can't we directly go for technology mapping? Like mapping the cells (muxes or flops) directly to a specific technology node instead of going for generic mapping in a separate stage? 2. Do we have any timing violations at the synthesis stage? Or is the design at synthesis stage timing clean?
1. There are some cadence internal generic blocks (ex cdn_latches as mentioned in the video) which tool places to understand and optimize the rtl better. 2. Yes, we need to do setup and power analysis at syn_generic step
Hello I have a doubt While creating clock you mentioned clock which is having period 20, inside -waveform you mentioned { 10 ,20 } Is that proper or we need to mention { 0, 10}
It can be (10, 20) also. It just means that first rise edge will be at 10ns and falling edge at 20ns. So here till 10ns, clock waveform will be low and it will rise at 10ns.
1. Foundry can create different versions of same cells based on doping: LVT --> Lower doping, less voltage required to turn on, better timing, poor leakage SVT --> Typical doping, normal voltage required to turn on, typical timing, typical leakage HVT --> Higher doping, higher voltage required to turn on, poor timing, low leakage Based on requirement of design, designer can enable these cells to get the desired specs. Disadvantage: Using multi VT will increase the cost as extra masks will be required. 2. The wafer has OCVs (on-chip variations) and hence, will not have same speed of PMOS and NMOS. In same area of wafer, PMOS-NMOS can be fast called as FF and in some area of wafer, PMOS-NMOS will be slower called as SS (Btw, other combinations are also possible) As we don't know where our chip will be present in the wafer, We have to make sure that the chip always works. So, that why we need to do analysis on multiple corners with derates.
Ma'am, its really really helpful. You have a great understanding of all these concepts. Looking forward for your upcoming videos. You are amazing..🙌😍
Thank you :)
This is best channel for the people who are started their carrier in VLSI.
Amazing content that you are providing, really appreciable your efforts and giving information freely to the people. If possible, please try to upload all the videos which are related these topics. Thank you madam 😘
Thank you for your kind words
Simple and very useful explanation in a very neat way.... Thank you ...
Please watch out Synthesis video here : ruclips.net/video/QvjIYxEmcNI/видео.html
Explanation was in detailed and good concepts
Watch out Physical Design concepts related videos here : ruclips.net/video/QvjIYxEmcNI/видео.html
Thank You🙏. Looking forward for upcoming videos
Great content. Thank you.
I have a few doubts though.
1. Why can't we directly go for technology mapping? Like mapping the cells (muxes or flops) directly to a specific technology node instead of going for generic mapping in a separate stage?
2. Do we have any timing violations at the synthesis stage? Or is the design at synthesis stage timing clean?
1. There are some cadence internal generic blocks (ex cdn_latches as mentioned in the video) which tool places to understand and optimize the rtl better.
2. Yes, we need to do setup and power analysis at syn_generic step
Really given clean information.. thanks you
superb explanation Thank you soo much!!
Very nice explanation..Very clear
Great explanation ❤
very well explained👏
Great information 👍
Thank you :)
It's really helpfull for me
Very nice explanation..
Tq so much got more clarity
Your videos are very helpful...please do more videos on CTS
Please watch out Synthesis video here : ruclips.net/video/QvjIYxEmcNI/видео.html
Hello I have a doubt
While creating clock you mentioned clock which is having period 20, inside -waveform you mentioned { 10 ,20 } Is that proper or we need to mention { 0, 10}
It can be (10, 20) also. It just means that first rise edge will be at 10ns and falling edge at 20ns. So here till 10ns, clock waveform will be low and it will rise at 10ns.
@@backtobasics5602 ok, thanks for clarifying my doubt.
Thank you 🤩
So nice speak
Hii, from which team we will get inputs to synthesis team
Finally
Will try to make videos more often😜
mam plz plz plz upload all the videos related to physical design flow.starting from netlist to gdsII
Mam can u plse exlain lvl hvt svt all cell function and ss technology and ff technology
1. Foundry can create different versions of same cells based on doping:
LVT --> Lower doping, less voltage required to turn on, better timing, poor leakage
SVT --> Typical doping, normal voltage required to turn on, typical timing, typical leakage
HVT --> Higher doping, higher voltage required to turn on, poor timing, low leakage
Based on requirement of design, designer can enable these cells to get the desired specs.
Disadvantage: Using multi VT will increase the cost as extra masks will be required.
2. The wafer has OCVs (on-chip variations) and hence, will not have same speed of PMOS and NMOS. In same area of wafer, PMOS-NMOS can be fast called as FF and in some area of wafer, PMOS-NMOS will be slower called as SS (Btw, other combinations are also possible)
As we don't know where our chip will be present in the wafer, We have to make sure that the chip always works. So, that why we need to do analysis on multiple corners with derates.
great. al videos are suoerbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb
Mam could u send ur mail id mam
For Physical Design related concepts subscribe to this channel : ruclips.net/video/QvjIYxEmcNI/видео.html