Видео

Hi, Are you not doing any technical videos ?..

Loved the way you are explaining... Thanks a lot.. very clean and clear cut information.. so much efforts.. really felt happy after seeing this video because I understood very clearly..

What is Isotropic and anisotropic ?

This is a really amazing explanation.. clear, clean, clarity.. superb.. you know? I really tried many times to understand this latchup and ended up with no meaningful understandings... Even I faced latch-up interview question.. but I couldn't able to answer it.. now I'm perfectly clear... Thanks for your hardwork..

excellent

This is dc and transient analysis

good lecture

great explanation

why you stop uploading videos

Excellent 👌

Excellent 👌

What happens to the charge present in M3 even though we have broken the path but still charge will remain on that metal , how will that path get a discharge path ? Another question is that while adding the diode how do we make sure the GND is connected as this process occur during manufacturing & at that time there is no electrical path present ?

Thank you so much mam ❤❤🙏

good ma

Thank youu

just wow!! Super clear explanation, thank you...

Crystal clear explanation. Perfectly understandable.

pichikeka

You have a very deep understanding of basics, this is simply an amazing explanation!!

Not clear

good oveview thank you.

hey can you please explain the timing_report generated by tempus for STA.

Excellent and very crisp explanation

how tapping reduces resistance?

now i clearly understood thank mam

Very nice coaching.

Great explanation ❤

Why antenna does not occur near drain or source

Thank you so much

very good explanation, thanks.

I think there is mistake of connection of diode between VDD and n-well. Shouldn’t that diode connected to input instead of VDD?

Can we create 2 or more skew groups for a single clock ? Is it acceptable or not for better skew minimisation

Very nice explanation..Very clear

Very nice..

good

can setup and hold both be negative at the same same time in same ff?

can addition of hold and setup time be negative?

Very nice

Very nice explanation..

Nice explanation

we dont have clock for latch right,, how D latch is depending on clock?

best explantions i ever seen

😢pls explained practically also

Please provide clock tree structure and explain skew balancing techniques and reducing insertion delay techniques

Can you explain how the die size ie width and height are decided with an example Like take an example you have netlist with 2lacks cells and now you need to initialize a floorplan decide height and width.

ruclips.net/video/7NctVo0BL3s/видео.html ...will be considered as forcing the logic into metastable state... this channel is not for children I guess.. Other I just understood "dewizors" is devices.

ruclips.net/video/MZiyk80X_0Y/видео.html OMG! The secret twister loop. You should learn basic electronics. Current never flows into a PNP transistor's base because that's current is in reverse direction.

mam really exalent expalaining mam tq u mam really before im struguling this topic mam now crearly understud mam tqu so much mam

why we need to have SDC file as input in Routing stage ? tool is not considering & using at anywhere in Routing stage ?

I have a doubt on it ,here both npn and pnp transistor are forming but in any transistor will activate by base region ,in above you are explained with emitter and base both are in same voltages and there is no conventional current at base region then who can transistor will on