for Level sensing, 16 transistors are required & a master-slave configuration. But this can be easily achieved using a simple D latch with 8 Transistors and an edge trigger clock generated by [(~A) & A] configuration
Hi. I found your video very useful and easy to follow to complete a school discussion. But I couldn't get your name to complete the citation (source referencing) of the video. I checked the about information but found no name apart from Back to Basics.
Hello Mam, it was really a nice video .. can you please let us know the meta stability in flops when their setup time and hold time is not met? it will be great help.
I have a doubt , in the waveform you explained after the clock turns high whatever data in D goes to Q but while explaining through diagram you said after clock turns high no input can reach from D
Thank you so much for the great explanation. It's very helpful (y). I have just one question, please! The setup time and hold time of an FF that are used to do setup&hold checks are the delay propagation of the data across the inverters inside the FF or something else? Thanks in advance, and waiting for new videos ;-)
I have both seen and read a number of videos and articles trying to explain what is probably the exact same theoretical thing, but each seeming to be slight variations of each other, and not just in terms of their symbology (which for such a technical field is very confusing for me). Does this article have it correct? learnabout-electronics.org/Digital/dig55.php
best EE vid I've come across in a year. simple and correct.
Instablaster
Very helpful!
Haven't learnt more in 8 minutes before.
just wow!! Super clear explanation, thank you...
Thankyou a lot mam....ur explanation is very simple , crisp, to the point and easy to understand.
Your videos helping me a lot... Thank you mam
Happy to hear that :)
It was just amazing...I can't express how helpful it was. Loved this video. Keep doing it mam.
the way you explain things are awesome mam looking forward for more videos.
Very helpful for basic STA.
Perfect explanation
Simply superb
It's a really good video....thanks ma'am
for Level sensing, 16 transistors are required & a master-slave configuration. But this can be easily achieved using a simple D latch with 8 Transistors and an edge trigger clock generated by [(~A) & A] configuration
Good explanation, thankyou
It's really useful. Thanks
Thank you, it's was Very helpful..
Vaya! en la India enseñan bastante sobre esto temas.
Thank you ma'm ,it is so helpful ❤️🔥
nice explanation
Very efficient and quick explanation
Thanks Mam...it was very helpful to me...I am expecting more videos in future like that...💐
Glad you liked it.Will make more videos in future :)
Thank you so much. I love you.
I have a question, in the positive level sensitive latch why do we need not gates in the diagram. time: 1:31
Super
Can you make a video on jk flip flop implementation using transmission gate
Hi. I found your video very useful and easy to follow to complete a school discussion. But I couldn't get your name to complete the citation (source referencing) of the video. I checked the about information but found no name apart from Back to Basics.
Hi,
I am glad that you found my video useful.
The channel name is "Back To Basics" and it is run by me "Deepali Thukral"
Very nice explanation.. I can help your channel with some concepts as well. I would like to join you for the explanation of new basic topics.
Mast!
Hello Mam, it was really a nice video ..
can you please let us know the meta stability in flops when their setup time and hold time is not met?
it will be great help.
Okay.. I will try to make a video on this.
@@backtobasics5602 Thanks
Hi Madam,
Generally latches will have enable pin, input and output
There won't be clock pin for latches.
we dont have clock for latch right,, how D latch is depending on clock?
I have a doubt , in the waveform you explained after the clock turns high whatever data in D goes to Q but while explaining through diagram you said after clock turns high no input can reach from D
Yup i like it
How reset work in flip flop please explain ma'am
Can you please make a lecture about Multi but flip flop concept madam
4:25 - 8:27
Hiiii madam can you explain about FSM ..
Thank you so much for the great explanation. It's very helpful (y).
I have just one question, please! The setup time and hold time of an FF that are used to do setup&hold checks are the delay propagation of the data across the inverters inside the FF or something else?
Thanks in advance, and waiting for new videos ;-)
You can see the videos that I have posted on setup time and hold time. That will answer your question. Thanks.
Yes, you are right. Your videos about setup time and hold time contain exactly what I'm looking for. Thank you so much.
Sr latches and Sr flip flop plz
I have both seen and read a number of videos and articles trying to explain what is probably the exact same theoretical thing, but each seeming to be slight variations of each other, and not just in terms of their symbology (which for such a technical field is very confusing for me).
Does this article have it correct? learnabout-electronics.org/Digital/dig55.php
:)