SR Latch Circuit - Basic Introduction

This video provides a basic introduction into the SR latch circuit. This circuit is a sequential circuit that stores memory - the output of the circuit doesn't depend only on the current state of the inputs but on the past history of the circuit as well.
Transistors - NPN & PNP: • Transistors - NPN & PN...
Operational Amplifiers:
• Operational Amplifiers...
LED Flasher Circuit:
• LED Flasher Circuit
RC Phase Shift Oscillator Circuit:
• RC Phase Shift Oscilla...
555 Timer - Pulse Generator Circuit:
• 555 Timer IC - Low Fre...
LED Blinking Circuit Using 555 Timer:
• LED Blinking Circuit U...
_________________________________
555 Timer Signal Generators:
• 555 Timer Signal Gener...
Diode Logic Gates:
• Diode Logic Gates - OR...
Transistor Logic Gates:
• Transistor Logic Gates...
Logic Gates and Truth Tables:
• Logic Gates, Truth Tab...
3 Input Logic Gates:
• 3 Input Logic Gates Wi...
______________________________
SR Latch Circuit - NAND Gates:
• SR Latch Circuit Using...
SR Flip Flop Circuit:
• SR Flip Flop Circuit W...
JK Flip Flop Circuit:
• JK Flip Flop - Basic I...
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[@TheOrganicChemistryTutor]

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@@robertmartens7839 okay edited

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[@utilizator1701]

7:17 ~Q=0 is a mistake.

[@mengvang396]

I don't think it is. Because if r and s are both 0, thus results in q having no change. (Not sure, don't trust my hypnosis, I'm an idiot)

[@kingbred01]

@@mengvang396 initially Q=0 & Q'=1 so it wouldn't change

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There is something so perfect about how this fundamental unit of memory looks like somewhat like an infinity symbol. Symbolically representing a never-ending loop.

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[@styxrakash4639]

At around the 10 minute mark, the very first of the rows of R,S,Q, 'Q(bar) shouldn't 'Q be 1?

[@LavishKamboj01]

When we release s and r which means we are cutting current connection then how can current flow in the circut(q=1).It is frustrating

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at 7:15 did you mean q bar should be 1?

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yeah it should be 1

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That's where I got confused too. Thank you. I think it should be a 1

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[@sammin5764]

R=0 s=0 Q=0 Qbar=0 !!!!!!!!????

[@grahamamir8579]

At 7:21. How comes the initial values noted, Q' is different from Q' on the diagram???
Someone answer please

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Thank you so much for this explanation, I needed to remember this....

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[@matthewjordan2814]

why does the initial S= 0 and R =0 not break everything. it makes my mind implode

[@Joaquin-l2q]

At around 07:00 I think you made a mistake with making -Q 0 instead of 1

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Why learn all this when you can program Arduino to do the same task?

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At 8:35, why didn't you feed the output "1" from the reset to the input of the set?

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[@luminous2585]

Out of curiosity, why does this schematic use two (inverse) outputs? For the record, I have very little knowledge of logic circuits, but there are two things that make this choice seem odd, which is why I'm asking for clarification. First, you hinted at it, but you don't know for sure what the initial state is going to be since it depends on which NOR gate feedbacks into the other one first. Second, we only need one output to represent all possible states because having both outputs be 1 or 0 at the same time isn't possible.
I didn't come up with this myself but saw a picture online, which is why I looked for more infos on the SR Latch in the first place. But it basically showed the S input simply leading into an OR gate, which then split up into the output and the other feeding back. Let's call the feedback F because this is confusing to write in text. Then the R input feeds into a NOT gate, which goes into an AND gate together with F, and the result goes into the OR gate from before. From what I can tell this should always initialize with the output as a 0, and it latches and resets all the same.
I have absolutely no problem with the explanation or anything. It's very helpful. I just wonder why it uses this format for the output.

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my school project is based on this circuit
i have implemenetd thuis circuit in Scratch for burglar alarm..... now my project has jus tbecome a wonder
thanks sir. I learned a lot

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Most importantly if q and q̃ are both 0 you can't revert it and won't get 1 on any of them ever again muhuhahaha

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How can a piece of wire 'remember' if they're 1 or 0? how long can a wire even remember if it is 1 or 0 even

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I watched few times and understood it.Thank you so muuuuuch for excellent presentation

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how can it save bit if all input goes to q? or the idea of save is loop inside?

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Or not gate. The way I remember it 1970 class?

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You have a video on SR latches but none on Laplace Transforms…

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7:19 how can Q and Q' have the same value ?

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