SR Latch | NOR and NAND SR Latch
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- Опубликовано: 19 апр 2015
- Digital Electronics: The Working of SR Latch
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+Neso Academy sir how can s=0 r=0 be a memory state when it is yielding two different outputs please explain
+Srinivas Paluri i think that when u are using nand gate then that is invalid case. but if u use the same case using nor gate, then that state is a memory state
it means that there wont be any change from the previous output if S=0 and R=0...kapish???
and S=1 and R=1 will be the memory state in NAND gate presentation....if u have doubt u may
draw the truth table of NAND gate and follow the steps that were done for the NOR representation
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The first time in my life I understand SR latch properly without leaving any doubts in my mind. Thank you Sir for your generous efforts.
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Well that was disturbing! Now I'm gonna have nightmares about that SR configuration.
Awesome presentation man! Thanks.
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This is probably the best explanation I've received for NAND & NOR gate SR latches. Great video!
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Watched 100s of videos to understand it but no one was able to teach like this
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When contradiction occur in logic: calm
When contradiction occur in digital logic: panic
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I have a question, why the input positions (S and R) are reversed for NAND Latch compared to NOR latch?
And also great explanation. You explained it better than any of the online sources I have been browsing!!
Sir, why we used 1 1 to check the memory condition incase of NAND SR latch?
Same doubt
Because latche made by using NAND gate has active High input conventionally
You are amazing! Ive seen so many related videos and only now i fully understand how latches work
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Why do the Reset in NAND SR latch is connected down, opposite to first case?
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Sir I have little confusion that why we interchange S and R while using NAND gate??
very helpful lectures..thaks NASO ACEDEMY
I did not know this was so simple.... until I saw this video... I am surprised to see this video was uploaded 7 years ago, yet it's so useful.... thank you so much!!!
Not even my professor in the university explained the subject this good! The written presentation is neat and clear. Awesome!
I would like to make a little comment though... Usually the SR latch using NAND gates are named as S*R* (Sbar Rbar) latches to prevent confusion.
When Set is 1 and Reset is 0; Output(Q) must be 0 ;Q' must be 1,but in NAND SR ,it's reverse,so S here is not Set?
Please elaborate.
I think he explained wrong...
@@darshanjaviya4770 yes I beleive so too, why flip S and R in the case of NAND gates? a high on the input S should always set Q to high, no matter which gates are used. S means "Set".
NAND is active low. that's why set=1 gives 0 at output
To help we named the inputs for a NAND latch S' and R' (the ' should represent a negator, because i cant draw lines over letters here)
@@AnasBashar as in nand gate we get the opposite result . to comply with that he has swapped them.
A million times thank you! :)
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thank you, from the bottom of my heart , thank you !
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11:01 That's the summary of my student life
Super helpful video, thank you! But I was not prepared for how disturbing case 3 is.
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That orgasmic feeling, when the concept clicks and you go 'aah'!!!
very clearly explained the topic and by removing confusion.
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Dude first of all thanks for the video.
I have a doubt, just after when you change the values of S and R after giving them 0 and 1 or 1 and 0... i.e., when you make both 0 why doesn't the values of Q and Qbar change, why does they remain same. I mean how did you make out that "previously Q is 1, input for one of Qbar is 1 so it will be 0".
Also dude what happens when initially both are 0?
Please reply
I'm really disturbed by the thing I saw...damn Q and Q'
😂
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