SR Latch and Gated SR Latch Explained | SR Latch using NOR gates and NAND gates

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  • Опубликовано: 24 дек 2024

Комментарии • 57

  • @shekharchaurasiya5236
    @shekharchaurasiya5236 11 месяцев назад +20

    Very very thank you for this awesome lecture. Everything came naturally one after another.

  • @ececse
    @ececse Год назад +14

    thankyou sir you made the concept crystal clear

  • @saddamalgafsi6721
    @saddamalgafsi6721 9 месяцев назад +6

    3:55 the output should be low instead of high, otherwise very good explanation, keep it up! 😁

  • @christopheracob3689
    @christopheracob3689 2 года назад +21

    I appreciate hearing the word circuit now unlike others they were pronouncing as cirkyut...

  • @poojashah6183
    @poojashah6183 2 года назад +7

    Thank you sir for making it premier so that we can ask you anything as you are available here

  • @KapilKumar-xz9ip
    @KapilKumar-xz9ip Год назад +3

    In the last example of gated SR latch with clock here sir use SR latch having NOR Gate and S corresponds to Q' & R corresponds to Q .
    that's why it is confusing sir, not mentioned it.
    Now what it again you can understand.

  • @karxxx02
    @karxxx02 Месяц назад

    Very nice explanation, u have also explained the concept based on which sr latch is made. Great

  • @sarabuvenkatasarayuharika7604
    @sarabuvenkatasarayuharika7604 8 месяцев назад +1

    Excellent explanation sir 👌😌

  • @mohammadrezajavadi3498
    @mohammadrezajavadi3498 Год назад +2

    Excellent explanation

  • @AndresRenePR
    @AndresRenePR 25 дней назад

    Definitely this subject is complex, best thing I can recommend that works for me, is to construct these with basic logic gates, and it makes more sense, I use Logisim to construct

  • @balajisriram6363
    @balajisriram6363 27 дней назад

    Very well explained thank you!!!!

  • @josedominguez2021
    @josedominguez2021 2 года назад +13

    Exelente explicación. Muchas gracias!!!

  • @mayurshah9131
    @mayurshah9131 2 года назад +3

    Please continue such informative and useful vedios,God bless you

  • @gryphon1538
    @gryphon1538 5 месяцев назад +1

    12:33 is the truth table correct??
    coz when s is 1 and r is 0 Q shall be 1 and R shall be 0...we can see when s' is 1 and r' is q is 1 on gated switch which has same nand gate..

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  4 месяца назад +1

      This is a truth table of the SR latch with active low inputs. That means S = 1 and R = 0, it will reset. That means Q = 0. (In active high SR latch, when S = 1, R = 0 then Q = 1)

  • @khannic2888
    @khannic2888 2 месяца назад +2

    great video completed

  • @koushikpendyala5214
    @koushikpendyala5214 Год назад +5

    In Gated SR latch using NOR, when E=1 and S,R =1 then you have said that the case is forbidden, but the inputs that are given are R' and S' so S,R = 0 must be forbidden? Also, The truth table for both Gated SR latch using NOR and NAND is same whereas it is different for SR latch using NOR and NAND? could you explain both these doubts.

    • @aiore6369
      @aiore6369 10 месяцев назад

      See the terminal brother...
      R output is Q not equal to R output is Q'

    • @studywithsalihaaashika5835
      @studywithsalihaaashika5835 Месяц назад

      Coz after the first NAND gate where the enable pin is located, the S and R for the latch in itself becomes 0 and 0, so for that case, the latch gives unprecedented values, henceforth the result being forbidden...

  • @uhuruplato5262
    @uhuruplato5262 Год назад +6

    Well explained.. And very clear.

  • @bhanuprakashagrawal2921
    @bhanuprakashagrawal2921 Год назад +1

    Great concept sir

  • @Yash........s-1-s4s
    @Yash........s-1-s4s 3 месяца назад +1

    Sir while applying inputs to combinational ckt is there any order to follow like msb to lsb or lsb to msb

  • @janu385
    @janu385 Год назад +1

    Sir, gated sr latch timing and level triggered flip flop. Are both same or is there any difference

  • @aryansilawal6477
    @aryansilawal6477 6 месяцев назад +1

    you said the inputs for sr transparent latch(using nand gates) are active low inputs and others are active high inputs.does this active low or high inputs have any correlation with the outputs we get (Q and Qbar).would you clarify this. its confusing

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  6 месяцев назад

      No, only inputs are active low. Consider the output as it is. For example, to set Q = 1, here for active low inputs S should be 0 and R should be 1. And likewise to reset the latch, S should be 1 and R should be 0. I hope it will clear your doubt.

  • @shilpapatel793
    @shilpapatel793 2 года назад +2

    Great 👏👏👏👏👏

  • @omerturnnn
    @omerturnnn Год назад +1

    Thanks for sharing with us. Can you tell me which software did you use for drawing timing graphics?

  • @6blak197
    @6blak197 9 месяцев назад

    3:04 explain about this 2 way switch

  • @flicksonj
    @flicksonj Год назад +1

    can i ask a doubt? why S and R have different timing.. sometime it has very duration.. sometime low. I am not an electronics student. its my complementary sub. so do you think is there something I needed to know? the timing is 26:48

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  Год назад +1

      Both S and R are different inputs. Many times in a bigger circuits, these inputs are the output of some other circuits. So, they may not be a same. That is why, if you see a time domain signal, then you may notice that, both S and R inputs are changing at the different times.
      I hope, it will clear your doubt.

  • @swayansamishra2284
    @swayansamishra2284 Год назад +1

    Hello sir at 3:56 how when S=1 then B=1!

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  Год назад +1

      Here we are assuming that, initially both S and R is 0. Now, when S is 1, then output of the first NOR gate becomes LOW. So, A = 0. And R is also 0.
      That means the output of the second NOR gate will become 1. And that's why B = 1. I hope, it will clear your doubt.

  • @MSQ819
    @MSQ819 2 года назад +89

    i'm totally confused now

  • @churchilokech4778
    @churchilokech4778 7 месяцев назад +1

    thank you so much

  • @thisissaroj941
    @thisissaroj941 2 года назад +3

    well explained...keep continue to upload so more videos i will support you dear😊

  • @nihar8783
    @nihar8783 2 года назад +4

    can you please provide slides

  • @Arj_s9
    @Arj_s9 2 года назад +4

    ❤️❤️❤️

  • @090-pranaykumar4
    @090-pranaykumar4 27 дней назад

    1. it would be so clear, if you explain what is meant by present state and current state. are both same?, if yes what is meant by present state in the truth tables, if you point out in diagrams and explain this, it would more clear.
    2. plz use even more better colour combinations in highlighting your cursor and the rows in truth tables.

  • @Ranbir.Bhardwaj
    @Ranbir.Bhardwaj Год назад

    A=0 when S=high
    But How is B=1 when S=high @3:47

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  Год назад

      It is assumed that, both S and R are 0 initially. And when S becomes 1 momentarily then both A and R will be 0 and hence B becomes 1. I hope, it will clear your doubt.

    • @Ranbir.Bhardwaj
      @Ranbir.Bhardwaj Год назад

      @@ALLABOUTELECTRONICS okay thank you

  • @amarsinghsidhu7028
    @amarsinghsidhu7028 6 месяцев назад

    Sir, Need derivation or source of diagram of SR latch because of confusion:
    Short connection from NOR gate A to NOR gate 2 vs Connection from NOR gate 2 to NOR gate 1.

  • @bharath_rbp
    @bharath_rbp Год назад

    Hello sir,
    Could you just explain what is active high and active low in brief? because it is getting hard to interpret these words

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  Год назад

      Active High means the input pin or the input signal will be active when that input is Logic '1'. (the input is active when its logic level is 'High')
      In the active low , the input pin or the input signal will active when that input is logic '0'. (Input is active when its logic level is 'LOW')
      I hope, it will clear your doubt.

  • @priyashalini6422
    @priyashalini6422 2 года назад

    Sir what about finite state machines kindly please do that video too

  • @cognitive_bits
    @cognitive_bits 8 месяцев назад

    kuch samajh nhi aaya

  • @ashikrevi
    @ashikrevi 2 года назад +2

    Watch some non- indian accent. This is important to your learning too. WTF