SR Flip Flop Explained | Truth Table and Characteristic Equation of SR Flip Flop

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  • Опубликовано: 24 дек 2024

Комментарии • 40

  • @chandanyogesh9475
    @chandanyogesh9475 10 месяцев назад +10

    ECE saviour 🙌🙏
    Thnks a lot sir

  • @mayurshah9131
    @mayurshah9131 2 года назад +19

    ALWAYS GIVING SOME THING SPECIAL, KEEP IT UP

  • @ALLABOUTELECTRONICS
    @ALLABOUTELECTRONICS  2 года назад +9

    For more info, check these other useful videos:
    1) Latch and Flip-Flop Explained
    ruclips.net/video/LTtuYeSmJ2g/видео.html
    2) SR Latch and Gated SR Latch
    ruclips.net/video/xONsaRVYQmA/видео.html
    3) Introduction to Sequential Circuits:
    ruclips.net/video/fLN1YOmuAr8/видео.html
    4) Digital Electronics (Playlist):
    bit.ly/31gBwMa
    Link for the Multisim Simulation :
    bit.ly/3tGWBuL

  • @anupamaajayan5522
    @anupamaajayan5522 2 года назад +12

    You are a life saver 🙌❤️

  • @mukuljaitu
    @mukuljaitu 7 месяцев назад +6

    Very helpful and informative videos.
    To the point, all things covered, excellent images and video quality. Literally I prepared for my exam in couple of hours from you the whole content of semester.
    Thanks bro, Sir ❤

  • @suyashagrawal9834
    @suyashagrawal9834 Год назад +19

    Its the only place where Gated SR latch is not called a Flip flop , all other places on either youtube or coaching classes call this gated latch a flip flop......... I don't know why people refrain from analyzing using timing diagram, I was so disheartened that such a basic thing is covered wrongly in all places..😢

  • @ChangeMaker0_0
    @ChangeMaker0_0 9 месяцев назад +1

    great lecture sir
    thankyou very much

  • @MurtuzaShaikh-z6g
    @MurtuzaShaikh-z6g 8 месяцев назад +2

    Sir i have a doubt, from the positive edge triggered SR flip flop,in the case where S=1 and R=1 why is the output of the AND gate 1 during clock transition period, and why is it becoming 0 just after clock transition, as just after clock transition, clock input would be 1, so 1 in both inputs of AND gate should be 1 na

  • @YdvSyAero
    @YdvSyAero 2 года назад +4

    Sir please also upload video on gated D-latch

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  2 года назад +2

      Please check this video:
      ruclips.net/video/EILb-DrYr8A/видео.html

    • @YdvSyAero
      @YdvSyAero 2 года назад

      @@ALLABOUTELECTRONICS I have seen .Thank you bhaiya . You are awesome

  • @6blak197
    @6blak197 9 месяцев назад

    S and R is present state right(that's what my understanding), then you have to copy the values of S and R in present state right, but you are making everything as 0 and 1 how?
    Just tell me how we are getting the present state values.
    I know about the first three rows 8:34 in present state, explain about the last 2 rows for present state.

    • @6blak197
      @6blak197 9 месяцев назад

      Understood myself sorry pal ✌️💪

  • @anonymous9217w2
    @anonymous9217w2 Год назад +1

    sir please reply why at 8:20 the flip flop get reset to 0 0 if S is 1 and R is 0., and why we measure Q and not Q'. Please reply.

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  Год назад +1

      Please check it once again, when S= 1 and R = 0 then flip-flop gets set to 1. Qn+1 is 1. (The fourth row)
      Regarding your second question, in the flip-flop design we are getting two complementary outputs. Some times Q' is also used in the circuits. For example, when you design a sequential circuits using Flip-flops then sometimes Q' output is connected to the next stage of the circuit (just to save one inverter)

  • @nayandutta8315
    @nayandutta8315 2 года назад +2

    Sir are you mr. Mohammed shanawaz sir from heritage institute of technology?sir please tell me. I am eagerly waiting for your answer.

  • @praveenkeshari2088
    @praveenkeshari2088 Год назад +1

    What a explanation... 🎉

  • @yusufislamkcr
    @yusufislamkcr 6 месяцев назад

    2:12 why the output of this xor gate is equal to 0? Maybe previous stage is 0. I didn't undarstate that.

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  6 месяцев назад +1

      Here, just for explaining, the initial state of the XOR gate is assumed as 0.

  • @guru6333
    @guru6333 Год назад

    Sir how sr flip flop using nand gate is different from this Nor gate sr flip flop?

  • @VaibhavC-co1bi
    @VaibhavC-co1bi Год назад +2

    Man you are amazing

  • @ajiteshkumar5841
    @ajiteshkumar5841 2 года назад +2

    Sir where are the videos of JK , T and D flipflop.

  • @khannic2888
    @khannic2888 2 месяца назад

    11:59

  • @MohidShaikh4444
    @MohidShaikh4444 10 месяцев назад +2

    Why are you talking like a robot? You always end each of your statements with the same tone. Not trying to be rude, just found it distracting.

  • @KandhanM-n1o
    @KandhanM-n1o 9 месяцев назад

    when the present state is 0 1 and the input changed to 1 1 now what is the next state of the sr latch or flip flop when enable is 1

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  9 месяцев назад +1

      S= 1 and R = 1 input is prohibited in the SR latch/flip-flop. Because when both inputs are 1, then Q and Q' is 0 at the same time at the rising edge. And after the rising edge, depending on the propagation delay, the output (Q and Q') will be either (1,0) or (0,1). I have already explained that from 8:33 onwards. Please watch it once again. You will get it.

    • @KandhanM-n1o
      @KandhanM-n1o 9 месяцев назад

      yes sir i got it thank you so much@@ALLABOUTELECTRONICS

    • @KandhanM-n1o
      @KandhanM-n1o 8 месяцев назад

      i got it sir thank u so much@@ALLABOUTELECTRONICS

  • @IronGreninja
    @IronGreninja 3 месяца назад +1

  • @tasadikapatel2
    @tasadikapatel2 Год назад

    Ur teaching is awesome bt can you use Hindi language also?????

  • @shashankkumar7141
    @shashankkumar7141 4 месяца назад +1

    Sir kmap was wrong

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  4 месяца назад +1

      Would you please mention where you are referring ?

    • @shashankkumar7141
      @shashankkumar7141 4 месяца назад

      In characteristic eq of SR FLIP FLPO

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  4 месяца назад +2

      @@shashankkumar7141 Its seems alright !! And the characteristic equation is also alright !! Just wanted to know, why do you feel its wrong !!

    • @rinturifle1488
      @rinturifle1488 3 месяца назад +2

      ​@@ALLABOUTELECTRONICS No sir, it's correct. 👍