Timestamps: 0:00 Introduction 0:52 Truth Table of D Flip-Flop 3:27 Timing Diagram of D Flip-Flop 6:20 Characteristic Equation of D Flip-Flop 8:05 Excitation Table of D Flip-Flop 9:17 Logic Circuit of D Latch, Gated D latch, and D Flip-Flop
what is the difference between a gated Latch and a flipflop? Is it only the clock transistion circuit that is present in flipflop and in gated Latch, there is only Enable Key ?
Some times it is required to connect multiple flip flops. ( e.g counters) So, in such case, some times it is required to connect the Q' output to the next stage. since you are directly getting the inverted signal( Q'), so there is no need to connect additional NOT gate. If you check the recent video of the ripple counter on the channel, you will get better idea, what I am saying.
I have explained that for SR latch in one of the video. It is also applicable for D latch. Please check this link. ruclips.net/video/xONsaRVYQmA/видео.html You will get the answer. In case, if you still have any doubt then let me know here.
In D flip-flop, the output Qn is same as D input at the rising edge of clock ( if it is positive edge triggered flip-flop). So Qn+1 will depend on the D input at Tn+1 th clock edge. I hope, it will clear your doubt.
It has been already covered. Please check the Digital Electronics playlist. Here is the link: ruclips.net/p/PLwjK_iyK4LLBC_so3odA64E2MLgIRKafl&si=L5DK9fTxesF3TtxS
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Timestamps:
0:00 Introduction
0:52 Truth Table of D Flip-Flop
3:27 Timing Diagram of D Flip-Flop
6:20 Characteristic Equation of D Flip-Flop
8:05 Excitation Table of D Flip-Flop
9:17 Logic Circuit of D Latch, Gated D latch, and D Flip-Flop
Greetings from Sabanci University, Istanbul/Turkey. Helped me a lot for my CS303 Logic course!
Your video made this topic crystal clear for me
I learnt the best way to deliver the electronics topics from you sir
Sir it will be a huge help if you bring an interview series of different exams ; discussing about solving these circuits intuitively
Your channel is underrated!
Very very nice 👌👌👌
Very nice 👍
Absolutely super
Hey man, welcome to you.
nice explanation sir
good explanation
2:11 I can not understand what YOU are saying here. I can not understand the clock
what is the difference between a gated Latch and a flipflop? Is it only the clock transistion circuit that is present in flipflop and in gated Latch, there is only Enable Key ?
Yes. Because of that, flip-flop is edge triggered and gated latch is level triggered.
@@ALLABOUTELECTRONICS ok sir thank you
Thank you
MDUians 🎉 here 🎉
how to design logic circuit with d flipflop if given any input 8bit?
DO we even need Q'? What's the use of that sir. Error detection?
Some times it is required to connect multiple flip flops. ( e.g counters)
So, in such case, some times it is required to connect the Q' output to the next stage.
since you are directly getting the inverted signal( Q'), so there is no need to connect additional NOT gate.
If you check the recent video of the ripple counter on the channel, you will get better idea, what I am saying.
Sir Digital Electronics के Objective Questions करा दीजिए BCA II Semester (राजा महेंद्र प्रताप सिंह राज्य विश्वविद्यालय अलीगढ़ से)
There is a seperate playlist on the second channel for objective questions.
Here is the link : ruclips.net/p/PLH9R5x7JVXCGT9tMPS1Ak6BhB1FPnKJvv
sericuitwtf seketi.....simple as that oh my god
what is the difference between d latch and gated d latch?
I have explained that for SR latch in one of the video. It is also applicable for D latch.
Please check this link.
ruclips.net/video/xONsaRVYQmA/видео.html
You will get the answer. In case, if you still have any doubt then let me know here.
@@ALLABOUTELECTRONICS I watched it before and learned gated versions are the ones that have enable inputs, so the difference is enable input?
I forgot the circuit diagram of counters and sequential circuits everytime.😢
How if the question is given to draw Qn and Qn+1..??
In D flip-flop, the output Qn is same as D input at the rising edge of clock ( if it is positive edge triggered flip-flop).
So Qn+1 will depend on the D input at Tn+1 th clock edge. I hope, it will clear your doubt.
@@ALLABOUTELECTRONICSThank you..Why the timing chart for Qn should be drawn 1 clock pulse after the Qn+1?
Jkms flip flop and Johnson counter
It has been already covered. Please check the Digital Electronics playlist.
Here is the link: ruclips.net/p/PLwjK_iyK4LLBC_so3odA64E2MLgIRKafl&si=L5DK9fTxesF3TtxS
Please upload T-flip flop
Yes, it will also be covered very soon.
You teach the topic incorrectly. You have drawn the timing diagram mix of latch and flip flop
I think probably you misunderstood it. Please let me know the timestamp where you are referring, so that I can clear your doubt.
how i really wish i understood this accent i mean, not to be racist though but ya^ll could try and differentiate Hindi and English