JK Flip-Flop Explained | Excitation Table and Characteristic Equation of JK Flip Flop

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  • Опубликовано: 11 янв 2025

Комментарии • 28

  • @ALLABOUTELECTRONICS
    @ALLABOUTELECTRONICS  2 года назад +6

    For notes on JK Flip-Flop, check this link:
    bit.ly/3cna9FP
    For more videos on Digital Electronics, check this playlist:
    bit.ly/31gBwMa

  • @SureshSuresh-jb6ju
    @SureshSuresh-jb6ju Год назад +7

    Just so much in one video and so much clarification 🙌🏻

  • @arkodasgupta0412
    @arkodasgupta0412 10 месяцев назад +3

    Sir in 18:34, you said that if the flipflop is level triggered, are you referring to latch here? Like I thought flipflops are always edge triggered and latches are level triggered. So JK Latch should encounter race around condition if clock pulse, J and K all are high at the same time. But JK flipflop, being edge triggered will overcome this racing around condition. Pls correct me if I am wrong.

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  10 месяцев назад +1

      Yes, what I mean to say was, instead of JK flip-flop if we have latch which is level triggered then race around condition is bound to happen. In case of edge triggered JK flip-flop, race around condition will be taken care.

    • @arkodasgupta0412
      @arkodasgupta0412 10 месяцев назад +1

      @@ALLABOUTELECTRONICS ok sir thank you

  • @seethapathysv4822
    @seethapathysv4822 3 месяца назад

    22:04 hi sir in this time you said that the flip flop is level triggered but in previous video you said that the flip flop work only if the clock is edge triggered.
    2. Finally you said the latch circuit can be converted into flip flop by clock transition in this case the circuit will be edge triggered or level triggered.
    Thank you for your video. Doing a great job :)

    • @boltzgaming4280
      @boltzgaming4280 28 дней назад

      I think he said IF the flip-flop was level triggered instead of edge triggered(which it usually is) then race around condition will arise.
      And yeah clock transition circuit will make the latch edge triggered as it is transitioning between levels.

  • @johnmuchori6605
    @johnmuchori6605 Год назад +8

    Very rich content. Thank you

  • @brundabatibarik9180
    @brundabatibarik9180 Год назад +2

    i'm finding trouble from 16:58 (positive edge triggered flipflop). can you please share the vdo where the clock mechanism has been explained.

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  Год назад

      Basically for the positive edge triggered flip-flop, at the rising edge of the clock, you need to see the value of J and K input. The value of the J and K input at the rising edge and the present output of the flip-flop ( just before the rising edge) will decide the next value of the flip-flop. Better you look at the D flip- flop video. In that also the timing diagram is explained. From D flip- flop timing diagram, you will easily understand the mechanism. And still if you have any doubt then let me know here.

    • @brundabatibarik9180
      @brundabatibarik9180 Год назад +1

      @@ALLABOUTELECTRONICS yes now I can make it out. Thank you so much for explaining everything in detail

  • @dheervira6269
    @dheervira6269 2 месяца назад

    8:29 - jk flip flop using nor gates

  • @DeviKhadka-b8b
    @DeviKhadka-b8b 3 месяца назад +1

    Best explaination

  • @vasue2849
    @vasue2849 2 года назад +2

    Just waiting for this

  • @nirbhayatiwari5425
    @nirbhayatiwari5425 2 года назад +6

    Bhaiya where can I ask doubts regarding any topics of electronics ???
    Btw the video of flip flops are awesome 👍👍

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  2 года назад +3

      You can ask the doubts in the comments.

    • @abhiramadapa7870
      @abhiramadapa7870 6 месяцев назад

      @@ALLABOUTELECTRONICS When you mentioned a flip- flop to be a edge triggered, again why are you considering a level triggered JK flip-flop(for race around ), there's no meaning at all instead you could call it JK gated latch with clk input right ?

  • @mayurshah9131
    @mayurshah9131 2 года назад +1

    Excellent 👍👍

  • @shacho6261
    @shacho6261 4 месяца назад +1

    very nice video

  • @6blak197
    @6blak197 10 месяцев назад

    Why 8:31 q is connected in both nor and nand ,to k?

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  10 месяцев назад

      Q' is connected to the NAND gate where J input is applied, while the Q is connected to another NAND gate where the K input is applied.

  • @sulaimana2230
    @sulaimana2230 2 месяца назад

    Sir , but u said flip flops only work at edge triggered and not level triggered then how are u saying this race around condition in jk flip flop to be due to level triggering? Please tell sir.

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  2 месяца назад

      Yes, although it is said to be a flip-flop. But it is actually a latch. If it is a flip-flop then you won't see that issue.

  • @a.romano3083
    @a.romano3083 Год назад +4

    equalt to... ziroo

  • @faraday6521
    @faraday6521 Год назад +8

    not understanding the explanation, you're too fast and i think you might be skipping some important explanation steps, thanks for the videos anyway.👍

    • @ALLABOUTELECTRONICS
      @ALLABOUTELECTRONICS  Год назад +16

      In case, if you find it little fast then I would recommend you watch it at 0.75 X speed with subtitles. .Also for better understanding the concept, it would be good if you watch the videos in a sequence in the playlist. It might help you. And still if you have any doubt then I am happy to help you.