JK Flip-Flop Explained | Excitation Table and Characteristic Equation of JK Flip Flop
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- Опубликовано: 10 июл 2024
- In this video, the JK Flip-Flop is explained in detail. In this video, the working of the JK Flip-Flop is explained using the logic circuit. And the excitation table and the characteristic equation of the JK Flip-Flop are also derived.
The following topics are covered in this video:
0:00 Introduction
1:41 Working and the Logic Circuit of the JK Flip-Flop
8:51 Characteristic Equation of JK Flip-Flop
12:07 Excitation Table of JK Flip-Flop
16:43 Timing Diagram of JK Flip Flop
18:05 Race Around Condition in JK Flip Flop
For notes, check this link:
bit.ly/3cna9FP
For more videos on Digital Electronics, check this playlist:
bit.ly/31gBwMa
Other useful videos related to Flip-Flops:
1) SR Flip-Flop:
• SR Flip Flop Explained...
2) D Flip-Flop:
• D Flip-Flop Explained ...
3) Latch and Flip-Flop:
• Latch and Flip-Flop Ex...
This video will be helpful to all the students of science and engineering in understanding the JK Flip-Flop.
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For notes on JK Flip-Flop, check this link:
bit.ly/3cna9FP
For more videos on Digital Electronics, check this playlist:
bit.ly/31gBwMa
Just so much in one video and so much clarification 🙌🏻
Very rich content. Thank you
Just waiting for this
Excellent 👍👍
Bhaiya where can I ask doubts regarding any topics of electronics ???
Btw the video of flip flops are awesome 👍👍
You can ask the doubts in the comments.
@@ALLABOUTELECTRONICS When you mentioned a flip- flop to be a edge triggered, again why are you considering a level triggered JK flip-flop(for race around ), there's no meaning at all instead you could call it JK gated latch with clk input right ?
Im confused. How come a flip-flop rolls back on itself?
i'm finding trouble from 16:58 (positive edge triggered flipflop). can you please share the vdo where the clock mechanism has been explained.
Basically for the positive edge triggered flip-flop, at the rising edge of the clock, you need to see the value of J and K input. The value of the J and K input at the rising edge and the present output of the flip-flop ( just before the rising edge) will decide the next value of the flip-flop. Better you look at the D flip- flop video. In that also the timing diagram is explained. From D flip- flop timing diagram, you will easily understand the mechanism. And still if you have any doubt then let me know here.
@@ALLABOUTELECTRONICS yes now I can make it out. Thank you so much for explaining everything in detail
Sir in 18:34, you said that if the flipflop is level triggered, are you referring to latch here? Like I thought flipflops are always edge triggered and latches are level triggered. So JK Latch should encounter race around condition if clock pulse, J and K all are high at the same time. But JK flipflop, being edge triggered will overcome this racing around condition. Pls correct me if I am wrong.
Yes, what I mean to say was, instead of JK flip-flop if we have latch which is level triggered then race around condition is bound to happen. In case of edge triggered JK flip-flop, race around condition will be taken care.
@@ALLABOUTELECTRONICS ok sir thank you
Why 8:31 q is connected in both nor and nand ,to k?
Q' is connected to the NAND gate where J input is applied, while the Q is connected to another NAND gate where the K input is applied.
equalt to... ziroo
equal to... wuan
will appear var... hiarr
not understanding the explanation, you're too fast and i think you might be skipping some important explanation steps, thanks for the videos anyway.👍
In case, if you find it little fast then I would recommend you watch it at 0.75 X speed with subtitles. .Also for better understanding the concept, it would be good if you watch the videos in a sequence in the playlist. It might help you. And still if you have any doubt then I am happy to help you.