Setup Hold time of a Flip Flop | Why does a Flip Flop requires setup and Hold time

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  • Опубликовано: 1 фев 2025

Комментарии • 59

  • @bobo_for_all
    @bobo_for_all 4 года назад +5

    Very nicely explained sir, I have never understand the word latch in Thanks for the that door explanation. You're example are easy to memorize
    Thanks for this video.

    • @TechnicalBytes
      @TechnicalBytes  4 года назад +2

      I am very glad to know that Videos are helpful to you..
      I have created a complete Playlist on FLip FLops and latches .. You can go through it. Link is given below:
      ruclips.net/p/PLPmSCnkkX4qvMfSrFZ70uXzUxmSdjU84c
      Please share your valuable feedback on them .. I am sure, these videos will open up your mind..

    • @bobo_for_all
      @bobo_for_all 4 года назад

      @@TechnicalBytes sure Thanks for this

  • @RandomHubbb
    @RandomHubbb 2 месяца назад +1

    Setup and Hold time of Latch itself (another video you did) and this one on top of that video, made me confused :D How does the setup and hold time of the individual latches are incorporated into the equation of the setup and hold time of the FFs? :)

  • @shashikantsingh4993
    @shashikantsingh4993 5 лет назад +14

    its good explanation , but if you had drawn the waveforms for Q1 and Q2 also it would have been much better to visualize it completely, btw thank you...nyc work

  • @ecerahuljain
    @ecerahuljain 5 лет назад +4

    Awesome explanation ! Plz Continue to make more video

    • @TechnicalBytes
      @TechnicalBytes  5 лет назад +1

      Thanks Rahul, i will keep posting new videos.. please keep commenting :) :)

  • @AVINASHKUMAR-yd1gp
    @AVINASHKUMAR-yd1gp 3 года назад +2

    So, The flip flop here is +ve Edge and the Latches inside are negative and Positive level triggered. Please confirm if I am correct

  • @AVINASHKUMAR-yd1gp
    @AVINASHKUMAR-yd1gp 3 года назад +1

    I have lost u after 12:16, why would Latch 1 with Negative level triggering pass D1 to Q1 after 1sec of Postive edge and in positive clock

  • @vikasgupta1665
    @vikasgupta1665 5 месяцев назад

    Hi Sir, I have one doubt. when we are calculating hold time then are we not considering propagation delay in the circuit?

    • @TechnicalBytes
      @TechnicalBytes  5 месяцев назад

      If you ensure that value is applied to flip flop before setup time, that means it reached to the output of first latch safely during level 0 of clock. Right?
      When positive edge comes I.e. level 1 of clock comes, latch 2 will start passing its input value (which is nothing but output of first latch) to its output. It will reach at output equal to 2nd latch delay. So, you can name second latch delay equal to flip flop propagation time, right?
      But when positive level of latch starts, because of not gate latch 1 is still active, it can corrupt its output, so during that time we need to hold input value I.e called hold time, right?

  • @Agigeorge1984
    @Agigeorge1984 5 лет назад +3

    wonderful explanation..thank you so much

  • @viveksikarwar1884
    @viveksikarwar1884 4 года назад +1

    Sir ji
    Can you re upload this explanation again
    As you described setup and hold in latch in very great manner.
    But in this that is not so much clear.
    If possible please do asap

  • @sunilht1990
    @sunilht1990 3 года назад +1

    Thank you so much for this video.

  • @harshverma3399
    @harshverma3399 5 лет назад +4

    thank you, sir : )

  • @harshpreetsingh1228
    @harshpreetsingh1228 4 года назад +2

    Amazing explanation, thank you so much

  • @joshuam8863
    @joshuam8863 3 года назад +1

    thank you!

  • @venkatvish9039
    @venkatvish9039 3 года назад

    Nice explanation!!!

  • @helpslabsocial916
    @helpslabsocial916 5 лет назад +3

    NIce explanation .. carry on

  • @manojkumar-oe6fs
    @manojkumar-oe6fs 4 года назад +3

    Sir,how come when the clock goes high and D changes within 1ns then Q1 changes?
    Because D will be propagated to Q1 only after 2ns right..
    Please clarify..
    Thanks in advance

    • @AVINASHKUMAR-yd1gp
      @AVINASHKUMAR-yd1gp 3 года назад

      If u got the answer please reply back, i have got the very same doubt after understanding what he meant to say. Thanks

    • @sandysandy6883
      @sandysandy6883 Год назад

      Hi! Yes to change the Q1 completely it needs 2ns sec but it can go into metastability state or unknown value so to keep the stable value at Q1 we cant change D within a 1ns window

    • @piyushnag6482
      @piyushnag6482 9 месяцев назад

      @@sandysandy6883 i think the question he was asking that even if it changes within 1ns if flip flop output is taking 2ns to change we cant say for sure whether that change will reflect in the output or not because flipflop is getting inactive meanwhile after 1ns

  • @pennapatipavankalyan9567
    @pennapatipavankalyan9567 4 года назад

    Thank u so much, sir. This is really helpful.

  • @sunilht1990
    @sunilht1990 3 года назад +2

    Can you please give idea on CDC from interview perspective. I mean on what condition what kind of cdc solution is required. whether it 2 stage, 3 stage, handshake or FIFO. I have been asked this question by on of TOP company for Senior RTL engineer position.

    • @TechnicalBytes
      @TechnicalBytes  3 года назад +1

      Sure dear, I am going to start a new series of videos on CDC design.

    • @TechnicalBytes
      @TechnicalBytes  3 года назад +2

      Dear, upon your suggestion I started a new series of videos on CDC. First Part:
      ruclips.net/video/7DoWQhfvAtQ/видео.html

  • @shivamporwal149
    @shivamporwal149 4 года назад

    very nicely explained!!!!!

  • @markfinn825
    @markfinn825 Месяц назад

    I have a data flip flop that doesn't need a set up.and hold time. It doe use extra parts though

  • @muhammadibnwahid6405
    @muhammadibnwahid6405 4 года назад +2

    Very well explained, thank you. May Allah have mercy upon you.

  • @rakeshreddy1365
    @rakeshreddy1365 4 года назад +1

    sir is masterslave flip flop pulse or edge triggered

    • @ayushgemini
      @ayushgemini 2 года назад

      master slave config is always edge triggered

  • @yadukrishanankrishnakumar3072
    @yadukrishanankrishnakumar3072 4 года назад

    Awesome explanation..

  • @ranveerdhawan5187
    @ranveerdhawan5187 4 года назад +1

    Sir can you make a video on difference between latch and a flip flop , here in starting of video the output of latch and flip flop is shown to be different as latch is working as level triggered and flip flop as edge trigerred , but I have read that a latch is without a clock and a Latch with clock is called Flip flop , please tell if I am wrong. Havenot reached the correct answer of difference between a Latch and a Flip Flop yet , please share your knowledge sir

    • @TechnicalBytes
      @TechnicalBytes  4 года назад

      Dear Ranvir, we have created a dedicated playlist on flip flop and latches .. I am sharing link here.. please go through it .. and let us know your valuable feedback.

    • @TechnicalBytes
      @TechnicalBytes  4 года назад

      Flip flop and latches playlist:
      ruclips.net/p/PLPmSCnkkX4qvMfSrFZ70uXzUxmSdjU84c

  • @tejinderkumar4344
    @tejinderkumar4344 5 лет назад

    Very nice

  • @divyakumarshah2498
    @divyakumarshah2498 5 лет назад +3

    Please make more videos

    • @TechnicalBytes
      @TechnicalBytes  5 лет назад +1

      Thanks and surely put more effort to meet your expectations

  • @ashishsontakke4040
    @ashishsontakke4040 4 года назад +1

    I'm here in 2020 July

  • @pavankalyanlakkireddy4358
    @pavankalyanlakkireddy4358 3 года назад

    due to so many adds your content did not reach people try to decreease adds

  • @AVINASHKUMAR-yd1gp
    @AVINASHKUMAR-yd1gp 3 года назад

    Don't mind but the explanation is a little confusing for a begginer, Please make a short script-type structure to avoid confusing sentences. Thank You for your efforts

  • @陳勁嘉-y5e
    @陳勁嘉-y5e 2 года назад

    tsao

  • @TejSingh-nh1uf
    @TejSingh-nh1uf 2 года назад

    Very nice