Hey vn v thanks for asking, In hold time , not gate delay is main reason for hold time if you can spend sometime on it and look again you can understand I hope this clears your doubt,if you have any doubts please feel free to comment.
Little confused with hold time the definition says that after the active edge of the clock data should be stable but here hold time is clock altering time can you please clarify it?
Thank you for such a nice explanation. Could you please tell me why the setup time corresponds to the delay of the latch(i.e., 2ns) and hold time corresponds to the delay of the not gate(i.e., 1ns) only and not the other way around.
Hey prajawal ,thanks for asking the question, Setup time corresponds to delay of latch. If that's other way then we will have more time relaxed for setup because clock is delayed .so this is not the critical case than above one. In hold time ,if corresponds to delay of latch, here also timing is relaxed so not gate delay is main reason for hold time I hope this clears your doubt,if you have any doubts please feel free to comment. Pls do subscribe it will me a lot 🙏 thank you
even if there was 1 ns delay during the hold time and the inout is changed it woulnd occur at the output right since setup time is 2ns and hence there will not be any change (@11:03)
In somecase,consider that Hold time error is 1Lakh,if setup time is zero then hold time also becomes zero.i dont know why it is happening like that.some guys are saying it is routing delay i can't get what is the concept behind it.
I am running a design in ISE..In place and route it will do timing analysis,i m right...In place and route phase setup time and hold time are shown... here for me setup time becomes zero and hold violation shows 164000 at last phase of timing analysis in place and route it also becomes zero i don't why it is not showing hold violation...it automatically makes zero..why it automatically makes hold time to zero
Every thing is wrong, Q1 should be transparent at negative edge and you are doing at positive edge that too you named it latch and talking it as a flip flop.
Thank you for the detailed step by step explanation.
Thanks🙏
Extremely 🙏🙏🙏. Thanks for clarifying this
Namaste 🙏 Aditya , thanks for the support, good luck and great health 👍😊
thanks for confirming my doubt
Good explanation for flop working and setup. But dint understand hold
Hey vn v thanks for asking,
In hold time , not gate delay is main reason for hold time if you can spend sometime on it and look again you can understand
I hope this clears your doubt,if you have any doubts please feel free to comment.
Good explanation. Thanks
Namaskaram nitish 🙏 , thanks for the support, good luck & good health 👍😊
Little confused with hold time the definition says that after the active edge of the clock data should be stable but here hold time is clock altering time can you please clarify it?
Thank you for such a nice explanation.
Could you please tell me why the setup time corresponds to the delay of the latch(i.e., 2ns) and hold time corresponds to the delay of the not gate(i.e., 1ns) only and not the other way around.
Hey prajawal ,thanks for asking the question,
Setup time corresponds to delay of latch.
If that's other way then we will have more time relaxed for setup because clock is delayed .so this is not the critical case than above one.
In hold time ,if corresponds to delay of latch, here also timing is relaxed so not gate delay is main reason for hold time
I hope this clears your doubt,if you have any doubts please feel free to comment.
Pls do subscribe it will me a lot 🙏 thank you
even if there was 1 ns delay during the hold time and the inout is changed it woulnd occur at the output right since setup time is 2ns and hence there will not be any change (@11:03)
There will not be any effect for hold at that case right ...
Hi great explanation can do video on hold time analysis once I am little bit confused with hold time equation.
i'm a bit confused since we are dealing with latches by regions do u mean level or edge region?
Namaskaram Sharan A , latches use level and Flop use edge,Thanks for asking, Good luck & Great Health _/\_ , Take care:)
Very good explanation
Thanks and welcome
But these delays are called as Tcq in Flipflop right ?
Can u answer me a question? is Asynchronous counter.....Synchronous sequential circuit???
No one ever answered me this question.......
Hey,
Can set up time be negative?
yes it can be
Namaskaram Girish _/\_ Thank you for answering, good luck & good health:)
Why maximum cumulative delay must be less than clock time period?
👌
In somecase,consider that Hold time error is 1Lakh,if setup time is zero then hold time also becomes zero.i dont know why it is happening like that.some guys are saying it is routing delay i can't get what is the concept behind it.
Hey karthi , thanks for asking but I am unable to get your question can you please elaborate 👍
I am running a design in ISE..In place and route it will do timing analysis,i m right...In place and route phase setup time and hold time are shown...
here for me setup time becomes zero and hold violation shows 164000 at last phase of timing analysis in place and route it also becomes zero i don't why it is not showing hold violation...it automatically makes zero..why it automatically makes hold time to zero
May be during optimization hold time got cleared this is my assumption I don't know exact scenario
Every thing is wrong, Q1 should be transparent at negative edge and you are doing at positive edge that too you named it latch and talking it as a flip flop.
Bro never mind.
If you could concentrate more on the concept rather than your fake accent, u could explain more proper and nicely.
Thanks Rajesh , I will improve on it , good luck, good health 👍😊
Thats how everyone improves....
Namaste 🙏, thanks for the support, good luck and great health 👍😊