Why a flip flop have setup time and hold time? Explained!

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  • Опубликовано: 23 ноя 2024

Комментарии • 36

  • @luaia2
    @luaia2 2 года назад +3

    Thank you for the detailed step by step explanation.

  • @vnnmichael
    @vnnmichael 4 года назад +2

    Good explanation for flop working and setup. But dint understand hold

    • @KarthikVippala
      @KarthikVippala  4 года назад

      Hey vn v thanks for asking,
      In hold time , not gate delay is main reason for hold time if you can spend sometime on it and look again you can understand
      I hope this clears your doubt,if you have any doubts please feel free to comment.

  • @kukatlapallivaralakshmi9650
    @kukatlapallivaralakshmi9650 Год назад

    Hi great explanation can do video on hold time analysis once I am little bit confused with hold time equation.

  • @adityapadhy1086
    @adityapadhy1086 2 года назад +1

    Extremely 🙏🙏🙏. Thanks for clarifying this

    • @KarthikVippala
      @KarthikVippala  2 года назад

      Namaste 🙏 Aditya , thanks for the support, good luck and great health 👍😊

  • @ayushgemini
    @ayushgemini 2 года назад +1

    thanks for confirming my doubt

  • @prajwalmp25
    @prajwalmp25 4 года назад +1

    Thank you for such a nice explanation.
    Could you please tell me why the setup time corresponds to the delay of the latch(i.e., 2ns) and hold time corresponds to the delay of the not gate(i.e., 1ns) only and not the other way around.

    • @KarthikVippala
      @KarthikVippala  4 года назад +4

      Hey prajawal ,thanks for asking the question,
      Setup time corresponds to delay of latch.
      If that's other way then we will have more time relaxed for setup because clock is delayed .so this is not the critical case than above one.
      In hold time ,if corresponds to delay of latch, here also timing is relaxed so not gate delay is main reason for hold time
      I hope this clears your doubt,if you have any doubts please feel free to comment.
      Pls do subscribe it will me a lot 🙏 thank you

  • @Nitishkumar1516713
    @Nitishkumar1516713 3 года назад +1

    Good explanation. Thanks

    • @KarthikVippala
      @KarthikVippala  3 года назад +1

      Namaskaram nitish 🙏 , thanks for the support, good luck & good health 👍😊

  • @nagulapatipoornasaipavanku1169
    @nagulapatipoornasaipavanku1169 Год назад +1

    But these delays are called as Tcq in Flipflop right ?

  • @vijaynammi648
    @vijaynammi648 3 года назад

    Very good explanation

  • @ShivaShiva-hm8qh
    @ShivaShiva-hm8qh 3 года назад +1

    Little confused with hold time the definition says that after the active edge of the clock data should be stable but here hold time is clock altering time can you please clarify it?

  • @bhanusashankreddy5013
    @bhanusashankreddy5013 4 года назад

    Can u answer me a question? is Asynchronous counter.....Synchronous sequential circuit???
    No one ever answered me this question.......

  • @sharana890
    @sharana890 3 года назад +1

    i'm a bit confused since we are dealing with latches by regions do u mean level or edge region?

    • @KarthikVippala
      @KarthikVippala  3 года назад

      Namaskaram Sharan A , latches use level and Flop use edge,Thanks for asking, Good luck & Great Health _/\_ , Take care:)

  • @nagendraprasad2890
    @nagendraprasad2890 2 года назад +1

    even if there was 1 ns delay during the hold time and the inout is changed it woulnd occur at the output right since setup time is 2ns and hence there will not be any change (@11:03)

    • @kotnitrinadh9581
      @kotnitrinadh9581 2 года назад

      There will not be any effect for hold at that case right ...

  • @saiprasadszhayi
    @saiprasadszhayi 4 года назад +1

    Hey,
    Can set up time be negative?

    • @girishgk395
      @girishgk395 4 года назад +2

      yes it can be

    • @KarthikVippala
      @KarthikVippala  3 года назад

      Namaskaram Girish _/\_ Thank you for answering, good luck & good health:)

  • @UECSaikrishnavaranasi
    @UECSaikrishnavaranasi 3 года назад

    Why maximum cumulative delay must be less than clock time period?

  • @kotnitrinadh9581
    @kotnitrinadh9581 2 года назад +1

    👌

  • @karthiv200
    @karthiv200 4 года назад +1

    In somecase,consider that Hold time error is 1Lakh,if setup time is zero then hold time also becomes zero.i dont know why it is happening like that.some guys are saying it is routing delay i can't get what is the concept behind it.

    • @KarthikVippala
      @KarthikVippala  4 года назад

      Hey karthi , thanks for asking but I am unable to get your question can you please elaborate 👍

    • @karthiv200
      @karthiv200 4 года назад +1

      I am running a design in ISE..In place and route it will do timing analysis,i m right...In place and route phase setup time and hold time are shown...
      here for me setup time becomes zero and hold violation shows 164000 at last phase of timing analysis in place and route it also becomes zero i don't why it is not showing hold violation...it automatically makes zero..why it automatically makes hold time to zero

    • @KarthikVippala
      @KarthikVippala  4 года назад

      May be during optimization hold time got cleared this is my assumption I don't know exact scenario

  • @rajeshsahoo1289
    @rajeshsahoo1289 4 года назад +1

    Bro never mind.
    If you could concentrate more on the concept rather than your fake accent, u could explain more proper and nicely.

    • @KarthikVippala
      @KarthikVippala  4 года назад +2

      Thanks Rajesh , I will improve on it , good luck, good health 👍😊

    • @user-lm1wu8ny8r
      @user-lm1wu8ny8r 3 года назад +1

      Thats how everyone improves....

    • @KarthikVippala
      @KarthikVippala  3 года назад +1

      Namaste 🙏, thanks for the support, good luck and great health 👍😊

  • @sunkararohith4481
    @sunkararohith4481 3 года назад +2

    Every thing is wrong, Q1 should be transparent at negative edge and you are doing at positive edge that too you named it latch and talking it as a flip flop.