Setup and Hold Time in Flip Flop | Digital Logic Design | Timing Issues in Flip Flops | GO Classes

[@GOClassesforGATECS]

Timing Issues in Flip Flops - Hold Time, Setup Time, Complete Playlist: ruclips.net/p/PLIPZ2_p3RNHi3p3cDBRInTHCJeITrkTFn&feature=shared

[@siddheshmadkaikar1645]

there is some magic in Deepak and Sachin sir's teaching! Concepts are hammered deep into the brain. Thankyou for this wonderful video. Take a bow!

[@umairalvi7382]

Awesome explanation sirrr.

[@GOClassesforGATECS]

Thanks and welcome

[@agoogleuser1341]

Thankyou sir

[@SK-qn5ry]

in short , during triggering edge of clock , neighbourhood of I/P (both left,right) must be steady .
Thats it from this video.

[@GOClassesforGATECS]

Yes. That's the summary.

[@AlivelammaJalla]

great lecture