So, if you have combinational circuit before the transmission gate, Thold should be Tcombo taken away from the time taken for transmission gate to turn off completely. Thold = Ttrasnmission - Tcombo Is it correct?
Lovely video! I had a request that can you make a video on Hold time analysis with multiple clocks . For example, what will be the hold time equation between a positively edge triggered launch flop and a negatively edge triggered capture flop. (both launch and capture flops having different clocks). Or is there a video already on it?
So, Hold check will be done at capture flop , it has to check whether data is stable after clock has reached it, whatever data that is lanched by lanched flop , after it got captured by capture flop. it should not moves so faster that it can collide with next data , it has to stable for Libray Hold time of capture flop .................... can anyone correct me ??
You see, presuming you understood why data launched at one edge is captured at the next edge, If I change data input at first edge, it will be captured at the second edge. Now, from this video, you know what the hold time of DFF is. Let us say, I changed my input at the second edge of the clock. If the arriving time of this data is less than the hold time of the DFF, the present input(at the second edge of arrival clock) is potential enough to change the past input(second edge of the capture clock). The whole phenomenon takes place at the second edges of the arriving clock and capturing clock. Hope it's clear.
Your videos are very informative and they clears most of the doubts. Thank you.
Your explanation is actually good
And very clear too
Thanks 🙏
Great explanation, this video clears all my doubts..Thanku for posting this type of content
Thank you very much. I finally understand this now.
Such beautifully explained!!
This video cleared my doubt thanks
Excellent videos
Wonderful explanation mam
very clear explanation
excellent explanation
very good. Thank you
can you do video on input files and sanity checks of physical design in every stage
Very informative video!!
So, if you have combinational circuit before the transmission gate, Thold should be Tcombo taken away from the time taken for transmission gate to turn off completely.
Thold = Ttrasnmission - Tcombo
Is it correct?
Please do videos about Dynamic and Static Power Consumption and methods to reduce power..
Sure.
Lovely video!
I had a request that can you make a video on Hold time analysis with multiple clocks . For example, what will be the hold time equation between a positively edge triggered launch flop and a negatively edge triggered capture flop. (both launch and capture flops having different clocks).
Or is there a video already on it?
nice video !
Thank you!
EXCELLENT
it's a nice explaination. Can you please provide video on latch timing anaysis?
Thanks.
Sure, will do a video on latch timing in future.
Thanks .ur video awasome
:)
Please do videos on static and dynamic power dissipation
Sure.
Thank you
Required time= tperiod + hold time? Correct me if I'm wrong
So, Hold check will be done at capture flop , it has to check whether data is stable after clock has reached it, whatever data that is lanched by lanched flop , after it got captured by capture flop. it should not moves so faster that it can collide with next data , it has to stable for Libray Hold time of capture flop .................... can anyone correct me ??
Thank you
Nice explanation mam
Why the hold check is same edge I can't undersood can You tell cleary once again if u don't mind
You see,
presuming you understood why data launched at one edge is captured at the next edge,
If I change data input at first edge, it will be captured at the second edge. Now, from this video, you know what the hold time of DFF is. Let us say, I changed my input at the second edge of the clock. If the arriving time of this data is less than the hold time of the DFF, the present input(at the second edge of arrival clock) is potential enough to change the past input(second edge of the capture clock). The whole phenomenon takes place at the second edges of the arriving clock and capturing clock. Hope it's clear.