Working of Depletion-Type MOSFET

Analog Electronics: Working of Depletion-Type MOSFET
Topics Discussed:
1. Similarities between depletion-type MOSFET and JFET.
2. Effect of increasing drain to source voltage on drain current.
3. Maximum drain current in n-channel depletion-type MOSFET and n-channel JFET.
4. Working of n-channel depletion-type MOSFET when gate to source voltage is 0V.
5. Working of n-channel depletion-type MOSFET when gate to source voltage is negative.
6. Working of n-channel depletion-type MOSFET when gate to source voltage is positive.
7. Homework problem.
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Music:
Axol x Alex Skrindo - You [NCS Release]
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[@shikhachaudhary5550]

Surely Id3 >Id1 >Id2 because of increment in no. Of e- , charge carrier +creses and hence i +creses.

[@VishalGupta-vr2ly]

the best explanation i had gone through many videos but this one is amazing

[@vireshmohan7554]

Id3>Id1>Id2

[@kamranali6645]

Sir! why the pinch off voltage is same for all the values of Vgs?
As we've seen that it changes in emosfet or jfet

[@shreyasn3078]

Thanks a lot for the lectures sir!! Very nice explanations. Could you please teach field theory also? It would help us a lot....

[@shubhamjaiswal4963]

watching 2 day before the exam and it is the best content of electronics

[@tsheringongmu1299]

mera exam kl h aur me aaj dekh rhi hu

[@AliRaza-be1bj]

​@@tsheringongmu1299mera bhi kal hai 😭

[@prashankbhardwaj5774]

Ty sir 4 it.this is awesome.keep doing this work.

[@fardeenahmed1147]

Thanks.... hope we will see some more tutorials

[@agstechnicalsupport]

Clear and to the point.

[@user-kn1ci7xb6o]

its a saviour for end semester exam
thank you sir

[@riteshraj7286]

what is the difference between N-channel D-MOSFET and E-MOSFET, explain with their transfer function and output characteristic.

[@picturization3914]

In case III where VGS>0, wouldn't it increase the depletion layer in the middle section of the N channel for the same reason, i.e. more reversed biased? If so, is it restricting the current ID in any way?

[@v.kfunstudio5195]

at VGs >0 minority carriers i.e, electrons will be accelerated ? With whom it will collide? electrons in the n channel or between themselves?

[@abhibham2588]

Id3 is (increase rapidaly & high ) as compare to Id2 & id1
Thank u sir

[@puneetpandey5451]

what is Vdd in case of n channel depletion mosfet

[@nasrinriya4242]

Amazing Sir thank you so much...Tomorrow is my xm..this is very helpful

[@varunrawat599]

Your welcome

[@mohammadzahidulislam3977]

You’ve watched this video 1 year ago. I'm watching 1 year later because of that LOG 🙃 @Nasrin Riya

[@nasrinriya4242]

@Mohammad Zahidul Islam bro chill..you will nail the exam this year.💙💙💙

[@mohammadzahidulislam3977]

@@nasrinriya4242 in sha Allah 💜 keep me in your prayers 🥰

[@debapriyadasgupta6534]

why didn't we have recombination in case of enhancement-type MOSFET?

[@rajgandhi4042]

Because in that case channel is not their from the beginning

[@kilarisreenivasprasad8030]

@@rajgandhi4042 THERE WE ASSUMED THAT WE MAINTAIN CHARGE NEUTRALITY...SO
REMEMBER DEAR BROTHER

[@jyothikorupuri2936]

sir should we take an insulator inplace of p type substrate

[@vijetasarswat9610]

Best explaination

[@anirudhmuthuswamy8091]

you said if we increase V(DS), after a point I(D) becomes constant due to reverse bias in the n-region under the drain. Why does I(D) increase in the first place if a reverse bias is present in the drain?

[@clutterphobic]

Same doubt I have... But nobody reply

[@juturubharathi8510]

Intially it has less depletion region but when we increase vds then depletion region also increases the hen id becomes constant and at the same time while keep on increasing vds at particular point there is a drastic change in the current.

[@ahanray]

I think that the reason for the increase in id is because of the fact that there is a potential difference between the Drain and the Source. Since the source is doped, we find an abundance of carriers willing to go to the drain causing a current id.
Now, extending this logic, when we further increase Vds the current increases but due to the decrease in conducting path, the resistance of the channel increases hence the current decreases.
The assumption is that the rate of change of voltage is smaller than the rate of change of the height of the depletion region.
I hope this helps.

[@bubunmazumder]

Sir,why inversion isn't occured in the case of case-2,i.e.,when Vgs is negative?

[@swapnildesai5622]

inversion will not occured becaause electrons attract posistive ions, and when Vgs is negative due to Sio2 layer positive ions occurs opposite side and dey is already positive charge becuz of p substrate , inversion will occurs only wen we apply Vgs.

[@changliu48]

May I know why with negative V_GS both electrons and holes are attracted and that was called recombination, but with positive V_GS only electrons are attracted and that was called collision?

[@ashimdas2207]

Electrons and hole attraction is called as recombination. And electron and electron repulsion is called collision... I hope you understand my point

[@rashitasingla9940]

same is my doubt

[@Anurag-fk3op]

Id3>id1>id2

[@vinayvinnu1282]

when vgs =0 how does the e- moving from n region through p substrate

[@parthmodi4181]

thankyouu so much sir

[@Alokkumar-tf8jq]

sir PN junction se to current flow hona hi nhi h..... to Depletion layer ki width increase hone se ID kaise level off ho sakta h.... clear kre jra

[@domithangeo876]

Can anyone know the general working and construction of D-MOSFET...AM LOOKING FORWARD TO IT...THIS ARE ALL N-type and P-type working

[@abhibham2588]

Domi Thangeo it will be not a passible for forward baised

[@saritaverma3974]

Best explanation

[@hanumantha1817]

Thanks bro...

[@artibisht370]

one more question...gate is connected through dielectric... metal (gate)/dielectric/ Metal.. its making capacitor right?so when we apply -ve voltage to the gate other side it must induce +ve voltage..so how canit repels electrons......am i right or wrong please clear..

[@dhirajkumarmewal4026]

Now make construction again with source and body terminal connected. what would you found, you must found that if V(gs) is negative then body terminal should positive, which is connected to p type substrate now holes will repel and electron will attract. try it, If you read it carefully you would surely find your answer.
By the way, Very good Question.

[@n.m2851]

how does pinch off occur at VGS = zero? in DE-MOSFET? nobody explains that

[@Infotainment-us8xz]

If gate terminal is insulated from channel how do the negative charge on gate repel conduction ē from channel
(when Vgs=-ve)

[@santhoshrapolu4067]

Actually an oxide is between the gate terminal and the channel, so it's operates same like a capacitor, so there generates a conventional current.

[@Infotainment-us8xz]

Santhosh Rapolu tanq

[@AwesomeMinds]

id3>id2>id1 because in case 3: when we apply Vgs>0v since gate is at +ve voltage it will attract electrons from the p-substrate thus making more electrons for the conduction.

[@mukutthakuria2687]

id3 > id1 > id2

[@hemkumarpatel4614]

siddharth you are right, it was wrong. by increasing reverse bias voltage, depletion width is going to increase.

[@siddharthkshirsagar2545]

sir at 6:09 you said with increasing reverse voltage the deplition region becomes narrow but actually it should be broad

[@Aman-Verma]

he said width of depletion region will increase and channel will become narrower .

[@swapnildesai5622]

reverse bias ,so depletion region is broad but channel of conduction is less ,like in jfet in reverse bias depltion increses and channel is dreaseses

[@sonikashyap4804]

right

[@chandrakanti3804]

He said that depletion region will become more thicker and channel through which current will flow will become more narrower

[@koppulapremsagar]

​@@swapnildesai5622Firstly go and learn the spellings of "Depletion , Increase and Decrease" plz.!!

[@SurajSingh-jc7hc]

Why did we short circuited gate and source here?

[@mikeejohnbaesa698]

thankyou so much. :)

[@GauravGupta-pb8mk]

Thank you sir

[@bpallavi8615]

Sir,in case-3 their will be a drastic or rapid increase in drain current as comparing to case-1 and case-2.

[@rakeshkota7531]

hai..sir
her sio2 is insulator...then how gate adding and attract the hole and elections..?

[@arpitgupta6710]

okay

[@Learner-lq3vu]

03:50 Isnt the current direction in depletion mosfet from drain to source

[@sameershirodkar3088]

Sir what about the p type depletion mosfet ... How is it different. . pls respond asap i have exams🙏🙏🙏

[@MobinSyd]

Please explain IGBTs

[@jeetendra1578]

id3 > id1 > id2

[@deeprobardhan3411]

Why gain source voltage of jfet cannot be positive? If positive .. it will produce more current in jfet ...

[@rahulsannigrahi8550]

Why Id current after increase become const why not it will decrease as the channel becomes narrow

[@jefferyaustin1571]

I am not sure what you try to do that you define Vg and Vd and place them in front of Vgs and Vds then take a loop without explaining how and what. Even though I took circuit analysis courses, but still could not understand what you try to do. Hope you can explain different ways and better. In fact, I understand why the channel becomes pinch-off.

[@susheelapatgar3640]

Thank u sir

[@advayargade746]

Thanks

[@bestcakesdesign]

Why we start study only by keeping V(GS)=0v not starting from V(DS)=0v

[@anonymouscaveman8557]

thanks sir

[@ahmedfrazafzal5239]

nice sir

[@prashankbhardwaj5774]

Anyone plz tell me that what is the work of silicon di oxide layer in this??

[@furqanmughal3462]

Prashank Bhardwaj due to silicon dioxide the input impedance of mosfet becomes very high

[@riyarajput8798]

Due to this input impedence will high and as well as we can say that sio2 also provides better isolation and it also behave as a good dielectric material that's why we use sio2

[@user-py6gx2gz8v]

thanks

[@parthmodi4181]

id3 is highest

[@swastikapremanandh6157]

what is Vdd here?

[@venkateshpolisetty5624]

id1>id2

[@artcetra445]

ID3>ID1>ID2

[@alterguy4327]

Id3 >Id1>id2

[@SachinSingh-gg9md]

nice...

[@hemanthgooty]

great

[@hamzazahid7768]

nice

[@saisumanth8064]

it is so simple (ID1ID3)

[@rishabhdevbanshi1299]

Id3 > Id2> Id1

[@phoenixop4673]

❤️🤝

[@leeeknowerrr1684]

❤

[@Rsapnavlog]

👍

[@sufyanch5853]

level (Y)

[@anassaifi7613]

Saviour

[@VishalSharma-ri3ih]

Id 3 > Id 1 >Id 2

[@bishnupriyarout3730]

I want p channel d mosfet

[@sonushaik1218]

Just change the substrate and wells

[@vishwajeetyadav810]

Same to

[@sonushaik1218]

Once go-to learning of electronics

[@sourabhrathour5080]

obviously... Id3>Id1>Id2...

[@user-ny4hm3mk2y]

i3 is higher than the rest two

[@saikumar-zw7bj]

Classes on 4G

[@lawrenceopoku6163]

great video.great work neso academy.God bless you.Jesus is Lord and he is coming soon.make him Lord of your life if you havent.

[@vibhorbhatnagar7074]

you keep on repeting same point again and again... from the begining from the begining.. u said it four times here and two times in last video... thats completly useless... cover main pouint rather than this

[@spacestars2340]

Id3>id1>id2

[@venkatrao404]

thanks sir

[@varunrawat599]

It's ok

[@MrJojija]

Id3 > Id1 > Id2

[@riyarajput8798]

Id3>Id1>Id2

[@uniqueversalunicorn2412]

Id3 >Id1> Id2

[@nfs_immortal]

Id3 > Id1 > Id2

[@md.omarfaruk8239]

Id3 > Id1 > Id2