Verilog Blocking and Non Blocking statements | Blocking Vs Non Blocking | VLSI Interview Question

[@Electronicspedia]

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[@vamosabv]

Thanks for this!

[@Yemo_naniartsanddanc396]

Good explanation🎉

[@Gary-kt8pd]

thanks, it's very clear and helpful

[@Electronicspedia]

Thank you 👍

[@jamiehuynguyen7259]

very clear, thank you so much

[@adityanarayanshukla9530]

Bhai Dhanyawaad

[@HG-jl4ed]

thank you so much sir understood the concept , can you please tell the difference in execution of the following i) #5 a=1; and #5 a

[@vidhya2965]

Thank you. Why blocking statement create race around condition?

[@gokulp6878]

this is the interview question
what will happen if we use non blocking to generate the clock
always clk=#5 ~clk
vs
always
clk

[@Electronicspedia]

Hi Gokul,
This question is kind of incomplete.
What is there in sensitivity list of always block? Is it *?
Or if sensitivity list depends on any other event like clock then behavior will be different.
I have simulated few scenarios in EDA playground. Please take a look.
www.edaplayground.com/x/f9ft
Regards,
Ravi

[@gauravrathi4278]

Non blocking one will make simulator hang

[@vamosabv]

@@gauravrathi4278 why is that?

[@ChiragHadiya]

sir we can't say at 1st and 2nd clk cycle value of b and c is 0..... ! it can be undefined means either 0 or 1 .right ?

[@mejaeuk1104]

감사합니다. Thank you!

[@susmithdas4312]

Sir what happens if we mix both of these statements in a block

[@Electronicspedia]

We are not supposed to use blocking and non blocking within one always block. This will give error when running lint and subsequently in synthesis tools.

[@gfsadds5574]

If you do synthesis , mixing them will not compile. However, if you do it in simulation, like inside an initial block in test bench, there are two cases:
1. a

[@tarekamrani7155]

System verilog please

[@Electronicspedia]

Sure will do on verilog and system verilog

[@umavathimarichetty2050]

always@(*)

[@Electronicspedia]

Was there any query?

[@AmanKumar-ph4my]

Hi sir can i get ur email id