#19 Blocking vs Non Blocking assignment | frequently asked during VLSI JOB INTERVIEW |Very important

in this verilog tutorial use of blocking and non blocking assignment has been covered in details with verilog code. Most of the time during VLSI Interview the common questions asked is what is the difference between blocking and non blocking assignment and when to use which ine.so I have tried to cover it thinking about VLSI Interview and design point of view . Blocking and non blocking assignment is one of the most important concept in digital logic design. it has been explained with verilog code and circuit diagram.
Lesson-1 Why verilog is a popular HDL • #1 Why verilog is a po...
Lesson-2 Operators in verilog(part-1) • #2 Operators in Veril...
Lesson-2 Operators in verilog(part-2) • Operators in Verilog (...
Lesson-2 Operators in verilog(part-3) • Operators in Verilog( ...
Lesson-3 Syntax in verilog • #3 Syntax in Verilog ...
Lesson-4 Data types in verilog • #4 Data types in veril...
Lesson-5 Vector and Array in verilog • #5 {Error:check descri...
Lesson-6 Modules and port in verilog • #6 Module and port de...
Lesson-7 Gate level modelling in verilog • #7 Gate level modelin...
Lesson-8 Dataflow Modeling in verilog • #8 Data flow modeling...
Lesson-9 Behavioral Modeling in verilog • #9 Behavioral modelli...
Lesson-10 Structural Modeling in verilog • #10 How to write veri...
Lesson-11 always block in verilog • #11 always block in V...
Lesson-12 always block for combinational logic • #12 always block for c...
Lesson-13 sequential logic in design • #13{Mistake:check desc...
Lesson-14 always block for sequential logic • #14 always block for s...
Lesson-15 Difference between latch and flip flop • #15 Difference betwee...
Lesson-16 Synchronous and Asynchronous RESET • #16(MISTAKE-Read Descr...
Lesson-17 Delays in verilog • #17 Delays in verilog ...
Lesson-18 Timing control in verilog • #18 Timing control in ...
Lesson-19 Blocking and Nonblocking assignment • #19 Blocking vs Non Bl...
Lesson-20 inter and intra assignment delay in verilog • #20 Inter and intra as...
Lesson-21 Why delays are not synthesizable • #21 Why delays are not...
Lesson-22 TESTBENCH writing in verilog • #22 How to write TESTB...
Lesson-23 Multiple always block in verilog • #23 Multiple ALWAYS bl...
Lesson-24 INITIAL block in verilog • #24 INITIAL block in v...
Lesson-25 Difference between INITIAL and ALWAYS block in verilog • #25 Difference between...
Lesson-26 if else in verilog • #26 if-else in verilog...
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Lesson-28 CASEX and CASEZ in verilog • #28 casex vs casez in ...
Lesson-29 FOR loop in verilog • #29 "for" loop in veri...
Lesson-30 WHILE loop in verilog • #30 "while" loop in ve...
Lesson-31 FOREVER in verilog • #31 " forever " in ver...
Lesson-32 REPEAT in verilog • #32 " repeat " in veri...
Lesson-33 GENERATE in verilog • #33 "generate" in veri...
Lesson-34 FORK-JOIN in verilog • #34 " fork and join " ...
Lesson-35 named block in verilog • #35 Named block in ver...
Lesson-36 TASK in verilog • #36 (MISTAKE-Read Desc...
Lesson-37 FUNCTION in verilog • #37 (MISTAKE-Read Desc...
Lesson-38 WIRE vs REG in verilog • #38 Wire vs Reg | when...
Lesson-39 FSM-MEALY state machine in verilog • #39 Finite state machi...
Lesson-40 FSM- MOORE state machine in verilog • #40 Finite state machi...
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[@paulchen355]

man, this guy nails it. I've been so confused about this shit for several weeks.

[@jitubaba5450]

One of the best explanation about blocking and non blocking assignment. Many many thanks

[@aftabbaig5367]

Nice explanation.
Its better to show the results (timing diagrams)

[@Sumit-pl8rq]

Very well explained. Keep up the good work.

[@adilbasu7183]

Thank you so much. Excellent explanation. Better than others.

[@circuitsanalytica4348]

Yes friend, really nice video

[@ajaymajhi8429]

Thanks a lot. Learned a important concept

[@marshalraju6089]

Thanks for this tutorial. It's very very helpful.

[@sp28769]

Tons of Thanks ❤ 🙏🙏

[@deepaksaraibhagi9612]

super.....very good explanation....

[@the_moonlight.23]

well explained, thanks

[@AjayKrews]

Super. Well done.

[@andyden8501]

Best explanation. ❤

[@bijaysah9135]

Good one . Thankx

[@harshakarthik9966]

15:23 how you are saying after second clock a =1 and b =0 ,its so confusing please explain it sir

[@ComponentByte]

If after first clock a=0, b=1(before clock transition takes place a and b got old value of b and al)
Before 2nd clock
a also got b value and b got a value and waiting for the next clock(2nd clock) to get updated value.
Thus after second clock
a=b means a=1
and b=a means b=0

[@harshakarthik9966]

@@ComponentByte thank you sir , also can you tell any source for preparing digital electronics mcqs for placements for freshers.

[@ComponentByte]

Please Visit testbench.in website.
There you will find many reference website name.
These websites are source of many things related to VLSI design.
www.testbench.in/links.html

[@joelmandebi7212]

Very great explanation

[@ComponentByte]

Thank you

[@vamosabv]

Thanks!

[@dooooo7188]

Good bro
Don't be nervous

[@ComponentByte]

Yes, you are true. I was new to youtube video making and that was also in English.

[@dooooo7188]

But it's fine

[@paulchen355]

@@ComponentByte Your English is better than some of my professors

[@reshmas3714]

Thank you sir

[@RoyAByers]

could you recommend any verilog book regarding knowledge

[@ComponentByte]

There are plenty of excellent verilog books freely available on internet by author not so famous. But the most recommended book is verilog book by Samir palintkar, freely available on internet.
I have read many PDF from unknown author.
I suggestion would be read book by Samir palintkar and then randomly read books by some random author.
If you search verilog book then you won't get good book. Type something like verilog FPGA design book, FPGA design book, verilog signal processing book, vlsi dsp verilog code book, verilog and vlsi signal processing book, practical verilog book. Thanks

[@saathwika7461]

As you said in side the procedural block, assignment statements executes sequentially, but here again you are saying assignment statements executes parallel in side procedural block.
Could you explain clearly.

[@ComponentByte]

Non blocking statements are executed parallely and blocking statements are executed sequentially inside a procedural block always. Hope it helps.

[@circuitsanalytica4348]

But in a procedure statements are executed sequentially, right?

[@maharshisanandyadav]

@@circuitsanalytica4348 ruclips.net/video/Fg761QGXUwU/видео.html

[@shubhamsrivastava7492]

same doubt to me also?

[@rahulsngh337]

@@circuitsanalytica4348 there are two ways to write procedural statements, always and initial....in always you can assign values in blocking or non blocking manner.....when non blocking the execution will be parallel...

[@shubhamsrivastava7492]

0.43, u r saying real hardware circuit always act in parallel. it should be series i guess, correct me if i am wrong.

[@ComponentByte]

Hardwares are parallel means they don't wait for anything. Incoming datas come continuously.if there is data dependency then they wait else Datas are overwritten and stored and processed.

[@ajiths1689]

nice video

[@chandanbhatt4778]

Blocking assignment is used in combinational ckt. whereas Non blocking assignment used in sequential ckt. Why?

[@ComponentByte]

Please watch my another video to understand it more.
ruclips.net/video/Vzj-Q_hdgcs/видео.html
If you still get query then I will try to explain your query

[@valobhediya]

Sir...
in two always @, the simulator choose which to evaluate first...but if the program is like this
a=1'b0; b=1'b1; reg out;
always @(posedge clk)
out = a;
always @(posedge clk)
out = b;
so the simulator chooses the output as either out = a (means 0) or out =b (means 1)...but why it doesn't choose out=x ?

[@ComponentByte]

The simulator may choose any value . out won't be X because values of a and b not equal to X.

[@valobhediya]

@@ComponentByte oh yeah...i didn't think of this😅

[@mathiazhaganvenkatachalam5414]

Hi sir, What's the difference between non blocking statement and fork and join

[@ComponentByte]

fork -join is parallel block concept and non blocking statement is assignment concept. So no similarity between these two. These are two different concepts.

[@alekhyakonuri252]

sir,can you please upload how to module insantiation make a video

[@ComponentByte]

I think I have explained in one of the video. Please check testbench video.

[@okokicici]

Nice way of explanation improve ur pronunciation 👍

[@ComponentByte]

Yes, you are right. I hardly use English in my day to day conversation so definitely I need to improve a lot while explaining things in English.I accept it. Thank you.

[@okokicici]

@@ComponentByte Good 👍
But ur explanation was awesome