For 5th question, all the statements will be executed in a single clock cycle irrespective of whether they are blocking or non blocking. The difference between blocking and non-blocking assignments comes into play when you have multiple assignments within the same always block, but across different lines of code. In the case of blocking assignments, they are executed sequentially in the order they appear in the code. In contrast, non-blocking assignments are scheduled to be executed concurrently after all the other assignments have been evaluated.
In Verilog, %name is not a valid format specifier and is treated as literal text in $display. Use %s to display strings, e.g., $display("Name = %s", name[80:49]); extracts and prints ASCII characters.
a full clock cycle contains 0 and 1, 11ns of 0 and 11ns of 1(as you can see Z value is flipping), combined to form a 22ns clock cycle. thus the period is 22ns.
@@dhavalpatel_98imo it's not 10.5*2, it's either 11*2 or 10 by 2, based on if simulator will round or truncate time for that delay. What if you had precision 0.1ns? Instead of 1ns, I wouldn't trust interviewer who is asking that question without running that code. My honest thinking answer should be , check LRM or run that code in a sandbox
Q3. P value is unknown because default value of reg is X, and reg is a 4 state variable (0,1,x,z) More over $display execute only once unless it is inside loop. Plz correct me If I'm going wrong
These questions are too simple. Real verilog interviews will be based on company specific modules and are upwards of 75+ lines of code (for anyone that cares)
Thanks 🙏 mam
For providing such a important questions with discuss
I use VHDL, and beginner with Verilog. Very nice tutorial 👍🏻
Thanks You. I think u r the first who r doing verilog code into the next level in you tube.
Thanks you so much Akash, keep watching ✌✌
your videos are very useful madam!
I am seraching for dv role
i have 2 yrs experience
it is very useful for me
Thanks for watching! Stay tuned ✌
kindly keep making these kind of questions....excellent videos and helpful also...thanky mam
Best video which totally based upon the questions on Verilog
Impressive 🎉
Thanks a lot!
For 5th question, all the statements will be executed in a single clock cycle irrespective of whether they are blocking or non blocking. The difference between blocking and non-blocking assignments comes into play when you have multiple assignments within the same always block, but across different lines of code. In the case of blocking assignments, they are executed sequentially in the order they appear in the code. In contrast, non-blocking assignments are scheduled to be executed concurrently after all the other assignments have been evaluated.
It does not take three clock cycles for Z to get the value of din in simulation; the update happens within one clock cycle. (5th one)
@2:11 format specifier must be ℅s instead of ℅name
Very great mam.thank you so much.keep uploading more videos like this in verilog interview questions
Thanks for watching Sindhuja, stay connected ✌
It's really helpful madam, Thank you 😍
Your efforts are really appreciated.....thanks mam.
Thanks for watching Tharun!
mam, answer of Q7 should be 4..... i think
because if fractional part is >= 0.5, it integer converts to integer+1
Yes i think 4 is correct
GOOD ..
Thanks
In Verilog, %name is not a valid format specifier and is treated as literal text in $display. Use %s to display strings, e.g., $display("Name = %s", name[80:49]); extracts and prints ASCII characters.
In the last question what will it be rounded up to 11ns and not truncated to 10ns ?
Thank you ma'am 😊
My pleasure Nikita, keep watching.
correct ans.10
Where to get such types of problem for practice
Mam Ur having good knowledge in vlsi right ,
Can i know which ru currently working in ?
correct ans.7
correct ans.9
Thank you mam...really loved it....
Thank you Mam...
My pleasure, thanks for watching!
Very Nice Video mam, for the last question why 10.5 ns rounds off to 11ns and not 10ns ?
For >=0.5 increment by 1
I am unable to join vlsi point telegram group
the problem is u dont clr peoples doubts in comment section,,,,u just likes the comment where people praise u
In 10th question..why we maltiplied 11× 2(why take 2 ).?
a full clock cycle contains 0 and 1, 11ns of 0 and 11ns of 1(as you can see Z value is flipping), combined to form a 22ns clock cycle. thus the period is 22ns.
to print the name use %0s not %name first ques
Ma'am verilog language complete krwa do jldi
Sure Ramesh
Make more vedios mam ....
$strobe($time -> is right not $strobe($rime is right
Kindly avoid small typing errors if it is understood
@@vlsipoint I can understand mam but not everyone will understand it know mam that's why I mentioned mam.
❤ 💙
please someone explain me the solution of qn. 5.
For 10th questions how you multiple 10.5*2, where this 2 came from, would you mind explain
@@dhavalpatel_98imo it's not 10.5*2, it's either 11*2 or 10 by 2, based on if simulator will round or truncate time for that delay.
What if you had precision 0.1ns? Instead of 1ns, I wouldn't trust interviewer who is asking that question without running that code.
My honest thinking answer should be , check LRM or run that code in a sandbox
Hi Madam, do some more question in Verilog
Sure Venkatesh, it will be uploaded soon.
ma'am don't use vibration in video ..it is very irritating
Nice video
Thanks
Q3. P value is unknown because default value of reg is X, and reg is a 4 state variable (0,1,x,z)
More over $display execute only once unless it is inside loop.
Plz correct me If I'm going wrong
For DFT ?
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$display("NAME = %name", ...) the compiler is reporting an error. Try %s
Mam why 11 is multiplying by 2.
Because 11 is only half period, period measures length of a full cycle 1-0-1
50Mhz
q6 one more error is that wire is not used for output, how can we assign without wire.
for output "out", by default Verilog will make it wire unless declared otherwise.
In question no.8 break is not used. All statements will execute
These questions are too simple. Real verilog interviews will be based on company specific modules and are upwards of 75+ lines of code (for anyone that cares)
Have you any channel for intermediate questions?
Nice ...any new videos for interview point of view