Blocking vs Non-Blocking Assignment | Lets Learn Verilog with real-time Practice with Me | Day 13

Learn Verilog with Practice : www.whyrd.in/s... Let's Learn Verilog with real-time practice.
Day14 : • Conditional Statement ...
Today's video resources:
HDLbits : hdlbits.01xz.n...
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[@S_R911]

Bro, i am saying that even my professors can't teach like you. You are a gem in teaching and i would really love the way you are making things simpler to be understood by us...Lots of Love💌💌💌

[@PilatesinSacramento]

Great session! The extra detail on blocking versus non-blocking (above what the HDLbits course included) were super helpful! The examples with variables a, b, c were helpful. But what really cleared things up as to why we have these two types of assignments was the shift register example. That made it totally clear why we need both types of assignments. Thank you!

[@whyRD]

Wow thanks a lot for detailed feedback… this means a lot …. Keep enlightening me once a while with such kind of detailed feedback. Thanks again ❤️

[@sangeetharamesh9979]

module clock_gen(output reg clock);
initial
clock = 1'b0;
always
#10 clock = ~clock;
Endmodule

[@Nishi_being_Nishiiiii]

Hi , I am enjoying these verilog series. Love your teaching. It makes it total fun to check our understanding by practically writing the code at hdlbits site. Just curious to know if you would teach System verilog anytime soon as well ?

[@Priya-tm2nh]

Good work 😃

[@Denilvaghasiya]

Good session bro.. keep it up

[@gayatri5397]

The third error is syntax error of always block, the always block does not have a sensitivity list