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module top_module ( input [1:0] A, input [1:0] B, output z ); always @(*) begin case({A,B}) 4'b0000: z=1; 4'b0101: z=1; 4'b1010: z=1; 4'b1111: z=1; default : z=0; endcase end endmodule thank you brother for making me use my brain to use concatenation here..... i found the above one to be the best alternative as we dont have grouping of kmps.

reached to last lecture 5th oct 2024

i have an idea to make it in nested loop but i cannot implement it

i have followed the same method , buy during optimization i am getting an error like "optim1 failed to simulate" . what is the view for doing optimization, currently i have selected emModel view ,

What about layoffs in intel ?

dude in the case statement we have to mention whether the condition is true or not...but y to declare them in bits 1'b1???? 1 means true and 0 means false ...so do we need to mention those true 1 and false 0 in bits always??????

plz upload the next video

sir i started this hdlbits thing but when i submit code it shows error "Status: Internal error. Unknown runtest exit status 25 Unknown runtest exit status 25. This shouldn't happen." how can i get rid of this please tell? and thank you for taking such initiative :)

Thanks

How could I contact you?

y always top module should be used as the name of the module ,,,, cant we keep our names bro???

Hi bruh now I'm in my final year of ECE. For AIML PYTHON IDLE VS CODE Microsoft Azure AWS TensorFlow Analysis of data set collection and training the dataset module file. For VLSI design automation tools, simulation tools, verification tools, layout tools, testing tools, DFM tools, software development tools, high-level synthesis tools, and IP cores. 1. Electronic Design Automation (EDA) software 2. Cadence EDA tools 3. Synopsys EDA tools. 2 to 3 years I want to use so give me a best latest for me brother. Please tell me as soon as possible.

For 2009 btech and 2012 mtech can try the vlsi job

Bro it was were will explanation. Bro how to learn vlsi from basic to advance

module top_module ( input a, b, c, d, e, output [24:0] out ); wire [24:0] top, bottom; assign top = { {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} }; assign bottom = {5{a,b,c,d,e}}; assign out = ~top ^ bottom; // Bitwise XNOR // This could be done on one line: // assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}}; endmodule

Can BCA graduates go in vlsi engineer domain.

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module top_module( input [2:0] a, input [2:0] b, output [2:0] out_or_bitwise, output out_or_logical, output [5:0] out_not ); assign out_or_bitwise = a | b; assign out_or_logical = a || b; assign out_not[2:0] = ~a; // Part-select on left side is o. assign out_not[5:3] = ~b; //Assigning to [5:3] does not conflict with [2:0] endmodule

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For wire4 problem. module top_module( input a,b,c, output w,x,y,z ); assign {w,x,y,z} = {a,b,b,c}; endmodule

Are you on insta ?

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bhaiya We want video on vlsi training vs GATE

At time 0 clk=0 en=0 a=0 b=0 At time 2 clk=1 en=0 a=0 b=0 At time 3 clk=0 en=1 a=0 b=0 At time 4 clk=1 en=1 a=1 b=1 At time 5 clk=0 en=0 a=0 b=1 At time 6 clk=1 en=0 a=0 b=1 At time 8 clk=0 en=0 a=0 b=1 because module top(); reg clk, en, a, b; initial begin clk = 1'b0; en = 1'b0; a = 1'b0; b = 1'b0; // Fixed $monitor formatting $monitor("At time %d clk=%b en=%b a=%b b=%b", $time, clk, en, a, b); #3 en = 1'b1; // Enable 'en' after 3 time units #5 en = 1'b0; // Disable 'en' after 5 time units $finish; end always #2 clk = ~clk; // Toggle clock every 2 time units always @(en) a = clk; // Assign 'a' the value of 'clk' whenever 'en' changes always begin wait (en) #1 b = clk; // After 'en' is set, wait 1 time unit and assign 'b' the value of 'clk' end endmodule

I think we need to consider out is an reg type

answer is D

Bro , need support to build skills for become a VLSI design engineer 😢🙏

Bro i am getting Electronic with specialization of VLSI Design and technology in NMIT college bengaluru which is comes under top 15 colleges in Karnataka. Should i join this branch

Bro i am getting Electronic with specialization of VLSI Design and technology in NMIT college bengaluru which is comes under top 15 in Karnataka. Should i join this branch

answer d

net will notstore, it is just change its state when we give an input, reg will store or hold the value untill we give next

this is the best tutorial for magic and basic digital design layout i've seen on youtube, thank you so much!

Give me some vlsi startup names

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Thank you

is it important to do m tech if i apply foe job and get exp as a b tech i guess it will work fine for me.

Thank you ❤

Thank you sir!

3:09 how u done that copy ??

Hey Hi please please Give me Gauidance ...I am Referring One book Verilog LRM in That Book I Can't Understand Chepter Number 15 ..... Please Suggest me Where I find Material Regarding Chepter no 15... Topic Name : "" Timing Checks using Stability Window"" And "Timing Checks and Clock Control " Example How To use $setup $Hold $skew $fullskew

Hi currently I'm sevicenow developer, I want to switch to vlsi now. Is it okay or recomended ti work from home?

I use Intel i3, is it okay if i upgrade RAM to 8gb and512gb SSD ?

bhaiya, plz upload the next video also.

Hi @whyRD, thanks for the great explanation. I have one quick question, I dont quite understand the AND gate operation Gates4 example, why does the AND output triggers high when the transaction is about to end?

Motivation ❎demotivation✅

thanks thanks thanks bro, i was very tensed to install all the open sources before watching this video. u have help me a lot not only in installing but guiding us in building a career in VLSI. i guess u are the only one who is clearly telling all the aspects and not only giving suggestions but also help us to learn by these kind of videos. its been only a week i subscribed ur channel but definitely i have made my mind to build career in vlsi by ur guidance. keep making more and more videos we will support u for sure. thanks again🤗🤗🤗

Good evening bro...thanks for your video...i have a confusion in it...i am a third year student...can you please suggest me the flow to study....for career as physical design engineer...waiting for your reply❤😊😊

What to do in 1st year in btech for VLSI

Why is my ngspice command showing error

I have some projects titles