#25 Difference between ALWAYS and INITIAL Block in verilog || VLSI interview question
HTML-код
- Опубликовано: 12 сен 2024
- Always blocks are called procedural block and it's a very useful constructs in verilog design. This tutorial explains how multiple always blocks are handled in verilog to avoid multi driver error in verilog.
Initial blocks are called procedural block and it's a very useful constructs in verilog design. This tutorial explains how initial blocks are handled in verilog and how initial blocks can be used effectively in verilog HDL.
Lesson-1 Why verilog is a popular HDL • #1 Why verilog is a po...
Lesson-2 Operators in verilog(part-1) • #2 Operators in Veril...
Lesson-2 Operators in verilog(part-2) • Operators in Verilog (...
Lesson-2 Operators in verilog(part-3) • Operators in Verilog( ...
Lesson-3 Syntax in verilog • #3 Syntax in Verilog ...
Lesson-4 Data types in verilog • #4 Data types in veril...
Lesson-5 Vector and Array in verilog • #5 {Error:check descri...
Lesson-6 Modules and port in verilog • #6 Module and port de...
Lesson-7 Gate level modelling in verilog • #7 Gate level modelin...
Lesson-8 Dataflow Modeling in verilog • #8 Data flow modeling...
Lesson-9 Behavioral Modeling in verilog • #9 Behavioral modelli...
Lesson-10 Structural Modeling in verilog • #10 How to write veri...
Lesson-11 always block in verilog • #11 always block in V...
Lesson-12 always block for combinational logic • #12 always block for c...
Lesson-13 sequential logic in design • #13{Mistake:check desc...
Lesson-14 always block for sequential logic • #14 always block for s...
Lesson-15 Difference between latch and flip flop • #15 Difference betwee...
Lesson-16 Synchronous and Asynchronous RESET • #16(MISTAKE-Read Descr...
Lesson-17 Delays in verilog • #17 Delays in verilog ...
Lesson-18 Timing control in verilog • #18 Timing control in ...
Lesson-19 Blocking and Nonblocking assignment • #19 Blocking vs Non Bl...
Lesson-20 inter and intra assignment delay in verilog • #20 Inter and intra as...
Lesson-21 Why delays are not synthesizable • #21 Why delays are not...
Lesson-22 TESTBENCH writing in verilog • #22 How to write TESTB...
Lesson-23 Multiple always block in verilog • #23 Multiple ALWAYS bl...
Lesson-24 INITIAL block in verilog • #24 INITIAL block in v...
Lesson-25 Difference between INITIAL and ALWAYS block in verilog • #25 Difference between...
Lesson-26 if else in verilog • #26 if-else in verilog...
Lesson-27 CASE statement in verilog • #27 "case" statement i...
Lesson-28 CASEX and CASEZ in verilog • #28 casex vs casez in ...
Lesson-29 FOR loop in verilog • #29 "for" loop in veri...
Lesson-30 WHILE loop in verilog • #30 "while" loop in ve...
Lesson-31 FOREVER in verilog • #31 " forever " in ver...
Lesson-32 REPEAT in verilog • #32 " repeat " in veri...
Lesson-33 GENERATE in verilog • #33 "generate" in veri...
Lesson-34 FORK-JOIN in verilog • #34 " fork and join " ...
Lesson-35 named block in verilog • #35 Named block in ver...
Lesson-36 TASK in verilog • #36 (MISTAKE-Read Desc...
Lesson-37 FUNCTION in verilog • #37 (MISTAKE-Read Desc...
Lesson-38 WIRE vs REG in verilog • #38 Wire vs Reg | when...
Lesson-39 FSM-MEALY state machine in verilog • #39 Finite state machi...
Lesson-40 FSM- MOORE state machine in verilog • #40 Finite state machi...
Difference between ALWAYS and INITIAL block has been covered in this verilog tutorial.
My mail id - email2vesystem@gmail.com
Please, don't send me mail asking for content(PPT,PDF) or any verilog code. For any other help you are most welcome.
**** Happy Learning ****
Don't forget to LIKE, subscribe 🔔 and comments.
Excellent. Thank you so much for this
Many many thanks.
Great explanation. I have a doubt at 11:16, can you please explain in detail why V4 won't change.
Thank you.
In both initial and always block V4 is assigned to a value at 2ns --> V4= 4
This is the only time V4 gets a value and after 2ns , V1,V2,V3 get new values because of their dependency on different variable after 2ns time. But V4 also depends on V3 but V4 = V3+1 is executed at 2ns and it remains same .
Let's say after last line if we write
#2 V4 = V3+1;
Then V4 gets new value again and that's at 8 ns and this value remains same until new value is assigned.
Consider this one
V1 value changes at 0ns then remain same and again changes at 4ns
If you want to learn more then execute the same programm for
1) always@(*)
2) always@(V1, V2)
It will solve all your query, if any
Hope it helps. Thanks.
@@ComponentByte thank you so much.
Sir , in the previous videos, you have mentioned that the statements inside the procedural blocks will be executed sequentially in the order in which they are written , so here why you said that the v1 and v3 will initialise at time t = 0??
V3 at 0ns means V3 is updated 0ns after V2 .
Sorry for the confusion.
@@ComponentByte means v3 will be executed after the v2 execution is completed, got it.👍
Yes.
Or you can say at same time both will be executed because there is no delay between V2 and V3
U said in always block we get back to first line after end of the statement that's why v1=1
But why it was neglected in previous lectures when u were giving always block ...plz explain.i am confused in this
Neglected in previous lectures means ? Please make it clear.
Or
You want to know why this happens ?
what is meant by synthesizable ,why always block is only synthesizable
Synthesizable code means the code represents a real optimized hardware. Optimized means the hardware designed is optimized in terms of power,time and area.
Something is synthesizable if the corresponding hardware get to know what exactly it's doing. So as per me ALWAYS construct is synthesizable because the hardware designed using always knows what exactly it's doing.
Thanks.
Always follow your videos thanks
You are welcome. Explore every possibility.
*Component Byte* Wow
Always block and initial block gets executed at t=0 ?? Or after initial block all always blocks get executed ?
Both the blocks are executed at t=0. They run independently and parallelly.
@@ComponentByte sir you mentioned in video that verilog ensures that all initial block executed successfully before running Any always block ?
always block is executed when it's signals (inside sensitivity list)are triggered but initial block is executed when program starts (it doesn't depend on sensitivity list) and at once.
This is what I meant. It tells initial blocks are independent of any signals unlike always block. So initial block execution starts before always block and this is what verilog ensures.
@@ComponentByte oh got it understood now thanks 🙏
Nice video. Last explanation is confusing.
Can you please let me know what caused you confusion .Thanks.
@@ComponentByte in the end when you were explaining with example..was hard for me to know which line of initial and always block you were referring to.
Yes, there is some confusion....
what is a procedural block pls explain?
It has been explained in tutorial -11. Please watch it. Still some doubt then you can post your query and I will explain. Thanks.
Procedure is a group of codes executed sequentially in the verilog module
It is important that everyone should understand what can be done in Hindi also. That's why you can use a little Hindi also. Just everyone should understand.
And thank you for it . And please complete this playlist fastly .
Thank you for the concern . The truth is I am neither good in English nor in Hindi. But yes I can speak both. One can easily find the grammatical mistakes in all my Tutorial. But my motive was to share my knowledge with maximum people and I choosed English. When I have to speak a lot i normally use Hindi(with flaws) because I feel comfortable(other than verilog concepts videos are in Hindi). So it's purely language barrier. Sorry , I can't do much. Hope you understand.
Sir I am not blame you for your language. My English is also very weak than you . I think same as like you. that concept is more important than language and you are perfect in your work that very good .
Please complete this playlist.
And make videos on RTL DESIGN ENGINEER.
INTERVIEW , JOB , COMPANIES , HOW TO BECOME .