Introduction to Verilog HDL using Free Software Icarus, GTKWave, and VS Code
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- Опубликовано: 24 апр 2022
- 00:03 What is Hardware Description Language?
00:23 Advantage of Textual Form Design
01:03 Altera HDL or AHDL
01:19 Just-Another HDL (JHDL)
01:33 VHSIC HDL (VHDL)
01:56 Meaning of VHSIC
02:30 Verilog
02:13 SystemVerilog
02:36 Test Bench
02:59 Logic Synthesis
03:06 Netlist
03:13 Verilog Modeling Styles
03:19 Gate-level Modeling
03:26 DataFlow Modeling
03:36 Behavioural Modeling
03:53 Verilog is case-sensitive just like C
04:06 White spaces, tabs, new lines are ignored
04:13 Keywords are lowercase
04:26 How to name a variable
04:36 System tasks or function starts with dollar sign
04:43 One line and multi-line comments
05:06 note on the old and new version of the syntax
05:13 module endmodule keyword pair
05:29 module name
05:33 port list
05:59 input and output keywords
06:19 Statements are terminated by semicolon
06:33 Icarus is Free and can be used offline
06:49 How to install iverilog
07:33 How to install Icarus for Windows
10:03 Where the verilog bin libraries or executables?
10:23 How to update PATH environment variables
11:46 How to check if iverilog is installed
11:56 How to view iverilog version
12:23 How to install Visual Studio Code Text Editor
14:06 How to customize or configure VS Code for Verilog
14:19 Verilog HDL extension
15:46 What is the purpose of GTKWave?
15:59 iverilog exe compiles the source files
16:06 vvp executable serves as the simulation runtime engine
16:59 How to create a verilog file using VSCode
19:56 module
20:17 half adder sample circuit using gate level modelling design
20:59 inputs
21:09 output ports
21:26 How to instantiate gates
23:23 How to write test bench
25:03 grave accent include compiler directive example
26:06 reg
26:53 How to declare output using wire keyword
29:43 How to code or set the values of inputs
30:03 timescale do not always default to 1 sec
31:26 How to save changes in dumpfile
32:06 vcd means value change dump
32:43 How to record top-level module wire signals using dumpvar
34:16 How to compile using iverilog.exe
35:16 How to simulate vvp file
35:56 How to view or display the timing diagram using GTKWave
38:29 digital circuits with multiple gates, wires, netlist
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I watched many videos..Finally this cleared all my doubts and i able to see waves..thank you so much..this is very clear explanation.. plz make more videos
This was a really awesome video. It helped me to get started with verilog!!!
AMAZING VIDEO I WAS SEARCHING FOR A COMPLETE ONE LIKE THIS ITS GREAT HOW YOU HAVE EXPLAINED!!!!!!
your tutorial video is clear enough and very helps, thank you👍
You are a good teacher. I watched tones of videos about the same topic but came out more confused. Consider teaching as a carrier because you have a talent. Thank you.
excellent video to get a student started. Thank you for this!
You are a legend in the making boyfriednibluefairy!
Very clearly explained and easy to understand the steps .. tq for the video it was helpful for the beginners to learn ..
Very nice discussion
excellent video!!
it was very useful thanks for create this video
helpful video, thanku
nice video, thanks!
very helpful
Thank you so much
The terminal "iverilog -v" worked but I still couldn't create file.vvp
Error: Include file half_adder.v not found
I tried removing the line `include "half_adder.v" but it still doesn't work
This introduction is amazing, all the steps are show, well done. Classic shitty tutorial are like "Setup your machine correctly, do 'make' in the console, thank you"
Try this if "verilog is not recognized as an internal command":
PRECAUTION: Close CMD.
1. Go back to "Environment Variables"
2. Instead of adding a new path to both of them like you did on this video, click on the label "Path"/"PATH" (depending on the way it looks
3. Double click on PATH / Path
4. Click on "Add"
5. Add your path
6. Do the same for both User and System Variables
7. Save
8. Use CMD to check if it's installed this time
hi, do you have a reference book for this? appreciate if you'll share it :)
You are great
@boyfriendnibluefairy Hello. After i use the iverilog -o half_adder_tb.vvp half_adder_tb.v command this pops up
"No top level modules, and no -s option.". I followed all the steps. Why did this happen?
Did you find the problem? I also had this problem right now.
In Quartus and other HDL IDE, when the terminal prompts "No top level modules..." This means the compiler is looking for a module or file (in our case .v file) that is responsible for accessing lower level files. The command above means iverilog is a command that is executed to compile "half_adder_tb.v" but remember that "half_adder_tb.v" needs to access "half_adder.v". This is what I can deduce from the terminal prompt. Is "half_adder.v" in the same directory with your test bench? If yes, does the character before the keyword include in the code the same as what is shown in the video? That character is beside the character 1 in your keyboard and not beside the return button...
The terminal process failed to launch: Starting directory (cwd) "C:\iverilog\bin\Verilog_tests\half_adder.v" is not a directory. Getting this error can you please help me troubleshoot this?
can you send me the step or the time stamp from the video where you encountered this error? thanks
I am not able to create the vvp file. I have added the path in environmental variables. I when i run the command it says invalid module instantiation. Please help
Can you type in the terminal "iverilog -v"? Is this command showing the version number?
11:46 my system showing iverilog is not recognised as internal or external command
What to do bro ...plz help me out 😭
reinstall the icarus and check the box (to yes) that says add path to executable thing
I just rebooted my pc and worked!
i have follow the verilog and vs code installation properly, i cant create a vvp nor vcd file. Please help for this fix thank you!
Can you type in the terminal "iverilog -v", if it's not working can you repeat the steps where you update the path of the library folder in the environment variables?
@endnibluefairy the terminal "iverilog -v" worked but I still couldn't create file.vvp
Error: Include file half_adder.v not found
I tried removing the line `include "half_adder.v" but it still doesn't work
Parabens.
Você poderia a partir desse exemplo gravar outro vídeo de como gravaremos esses arquivos no Fpga ex:(Altera, Xilinx, Lattice ICE40, Tango, etc).
Soon someone will teach us how to upload/burn this to a Lattice device, hopefully I'll be able to create a video on that. Thanks for the suggestion
half_adder_tb.vvp: Unable to open input file.
facing this problem any soln
The input file of half_adder_tb.vpp is "half_adder.v" (you use include keyword inside the testbench). Is "half_adder.v" in the same directory with your test bench? If yes, does the character before the keyword include in the code the same as what is shown in the video? That character is beside the character 1 in your keyboard and not beside the return button...
around 35 min it is showing error while typing iverilog -o halfadder_tb.vvp halfadder_tb.v that iverilog is not identified as the name of cmdet
unable to get the .vvp file . It says: half_adder_tb.v: No such file or directory
can you send the step or the time stamp from the video where you encountered this error? thanks
I am getting unable to open vpp files. I have followed all the steps.
what does the error say? I'm thinking of two possible reasons. 1. the location of vpp executable is not added in the environment varibales. 2. the location of your .vpp files and your current terminal directory is different
I tried to run the same but got this error message
"Include file half_adder.v not found"
Is "half_adder.v" in the same directory with your test bench? If yes, does the character before the keyword include in the code the same as what is shown in the video? That character is beside the character 1 in your keyboard and not beside the return button...
okay, for those who are having trouble with iverilog is not a recognizable blah blah blah
e
all you need to do is add the iverilog/bin directory to the path on this pc>advance system settings> environment variables under user varibles, double click "Path" and paste the iverilog/bin same with system vaiable "Path"
but now... im having another problem creating .vvp file its giving me a message "No top level modules, and no -s option."
any help?
when you execute "iverilog -o filename.vvp filename.v" were you able to create .vvp file? If you have a lot of .v files in one folder, chances are, you have a lot of modules. iverilog is confused which among these modules is the top-level module. Or if you don't have a .v file in the current directory, then it cannot locate any module at all.
If you have a lot of modules, for example file1.v file2.v file3.v and among these modules file2.v is your top module then you should execute "iverilog -o filename.vpp -s file2.v"
@@boyfriendnibluefairy at 35:00 i am getting error it is showing that half_adder.v: No such file or directory .I am not able to create the vvp file .can you please help me?
Did you find solution to this problem?
No bro can you please help me
Is "half_adder.v" in the same directory with your test bench? If yes, does the character before the keyword include in the code the same as what is shown in the video? That character is beside the character 1 in your keyboard and not beside the return button...
My code is not creating a vcd file. Is there any fix?
The vcd file should be created after the vpp command. Can you view your folder in terms of "details" instead of "list" just to make sure the extension is not simply hidden in plain sight?
How to create tb file for sample_circuit?
Perhaps we should stick we with "sample_circuit_tb.v" and also the same name inside the code for module name because I'm not sure with the algorithm of Icarus
In iverilog folder in my laptop vcd, vvp file are not created. can anybody help me with this
It's not necessarily in the iverilog folder, it's supposed to be in the same directory with your .v file. Another possbile reason is the sequence of file names in the command specified at time stamp 34:49. If it's still not working can you reply the error messages here?
@@boyfriendnibluefairy same problem ive checked the sequence but the vvp file is not showing
@@justinrangad9065 can you try saving the files in your users director, for example C:\Users\\Desktop I'm not sure if this has something to do with access issues in some directory. Also, try to reinstall iverilog libraries in a new directory, then update the new location of those libraries in your path variables. I'm not sure if some of your directories have restricted access. Also, try to show hidden folder/files in a directory. Or the file is there, your OS just hide the extension .vpp
@@boyfriendnibluefairy I fixed it. It was a problem with the environment variables. I made a mistake. Thanks for your help keep up the good work 🙏
@@justinrangad9065 can u tell me what kind of problem in environment variable, because i am facing the same problem
hello brother , vvp half_adder_tb.vvp : after this it shows unable to open input file
at step 35:36, did you generate a .vcd file? Not sure how to fix your problem, can you just reinstall the libraries then restart your computer, before using the vvp command...
Error
'a' has already been declared in this scope.
It was declared here as a variable.
'b' has already been declared in this scope.
It was declared here as a variable
And this is what I'm getting in the terminal.
And in Problems
Include half_adder.v not found iverilog.
I'm not sure what's causing the problem, can you just change the name of your variables. And then transfer all files into one folder
where can i get this code?
I already lost those files, perhaps one can just type it from scratch. Sorry
Can we generate saif file using this software
not tried it yet
Paano naman po pag full adder gagawan? May you guide us again po sir?
I apologize, just got very busy these days... Perhaps you can look for any schematic diagram of full adder then begin constructing it starting at the guide 16:59.. Maybe in the future I can create a guide on how to code full adder using 2 existing half adder...
@@boyfriendnibluefairythis actually helped me so thanks a lot sir! I hope you get to create contents about this topic.
When I compile I got a error saying
“The term iverilog is not recognised as the name of a cmdlet,function or operable program”
What should I do ?
Add the directory of iverilog to environment variables. If you've done this already, maybe you saved your .v files in a restricted directory. Try to save verilog files in your user directory like C:\Users\\Desktop
@Beena is your issue resolved??
@@RahulKumar-oz2mc I was not the one who asked this question but I got the same issue discussed here. After adding my file in C:\Users\\Desktop it worked as expected.
@@boyfriendnibluefairy faced same issue, added in environment variable and also saves in C:\.... but getting the same error iverilog is not recognized
@@renumehta2503 , can you transfer the installation to "C:\Program Files\iverilog" and update everything else based on this new installation folder. If iverilog is still not recognized after this, try to forcibly execute the iverilog application using absolute path. For example, in the command prompt: "...> C:\Program Files\iverilog\bin\iverilog -o filename_tb.vvp filename_tb.v", let's see if it works...
I am getting a problem with saving my code
Hi Pemmaka, not sure what exactly the problem is without the step by step procedure. Here are my guess solutions:
1. You may close VS code and then restart your entire computer and then try it again.
2. The directory of the verilog libraries was not saved or was incorrectly saved in the environment PATH variable.
3. Kindy remove the verilog extension from VS code and then reinstall the extension again.
4. Uninstall old VS code and then install an updated VS code.
Hope it helps
@@boyfriendnibluefairy thank you
So your from the PH too sir?
Yup
very good video..while creating vvp file. It says syntax error
C:\iverilog\bin> iverilog -o half_adder_tb.vvp half_adder_tb.v
./half_adder.v:2: syntax error
solved
@@marshalbasnet2454 facing same issue with "error half_adder_tb.v:2: syntax error
I give up." kindly help
14:30
Adding the ivariable enviroment variable doesen't add it to the path, you have to add it the the path
Btw. good video
bro good day. filipino here, need your help right now about verilog, is there any way i can contact you?
"D:\iverilog_test>vvp half_adder_tb.vvp
ERROR: half_adder_tb.v:13: $dumpvars cannot dump a vpiConstant. "
its showing this error
Not sure how to fix that problem... In the video at time 32:54 , did you deviate naming some variables? or did you use for loop in changing the values of a and b? I read somewhere that dumpvar have issues in handling array of variables and for loop. In the prompt, you have problem at line 13, can you play around with the .vcd file name, can you use a new file name for that file?
I have this problem, help me
PS C:\iverilog\bin\iverilog-test> iverilog -o half_adder_tb.vvp half_adder_tb.v
iverilog : The term 'iverilog' is not recognized as the name of a cmdlet, function, script file, or operable program. Check the spelling of the name, or if a path was
included, verify that the path is correct and try again.
At line:1 char:1
+ iverilog -o half_adder_tb.vvp half_adder_tb.v
+ ~~~~~~~~
+ CategoryInfo : ObjectNotFound: (iverilog:String) [], CommandNotFoundException
+ FullyQualifiedErrorId : CommandNotFoundException
I'm not sure what Operating system you are using. Add the directory of iverilog libraries to environment variables. If you've done this already, maybe you saved your .v files in a restricted directory. Try to save verilog files in your user directory like C:\Users\\Desktop. Also check the filenames. Hope that helps
@@boyfriendnibluefairy No meu caso windows 10 64 bits tinha esse mesmo erro . Então instalei a ultima versão do Icarus verilog e resolveu
@@fonecelautorizadatim882 Thank you for the solution
PS C:\iverilog\bin\iverilog_programs> iverilog -O Half_Adder_Testbench.vvp Half_Adder_Testbench.v
iverilog : The term 'iverilog' is not recognized as the name of a cmdlet, function, script file, or operable program. Check the spelling of the name, or if a path was included, verify that the path
is correct and try again.
At line:1 char:1
+ iverilog -O Half_Adder_Testbench.vvp Half_Adder_Testbench.v
+ ~~~~~~~~
+ CategoryInfo : ObjectNotFound: (iverilog:String) [], CommandNotFoundException
+ FullyQualifiedErrorId : CommandNotFoundException
Please help me this error.
Hi Aditya, Have you resolved this??
Can you type in the terminal "iverilog -v", if it's not working can you repeat the steps where you update the path of the library folder in the environment variables?