Verilog Operators | How to trigger an always block | SR Flip-Flop Example

Lecture about Flip-Flops: • SR Flip-Flop, D Flip F...
00:03 Concept of Concurrency in Verilog
00:23 What is the purpose of assign keyword
00:29 What is a net?
00:39 How to trigger an always block?
02:09 Verilog Arithmetic Operators + - * / %
03:03 Verilog Logical Operation, Counterpart of Logic Gates Connections
03:43 Verilog Equality and Inequality Symbols
04:16 Verilog Bitwise Operators
04:39 Verilog greater than or less than operators
04:49 Verilog Shift Left and Shift Right
05:16 timescale compiler directive is for time unit measurement for timing diagrams
06:13 posedge clock pulse event control for triggering always block
06:43 negedge keyword means a transition from 1 to zero or x or high impedance z
06:53 blocking vs nonblocking assignment
07:33 Continuous Assignment vs Procedural Assignment
07:46 forever keyword used in executing a looping statement
07:53 $ finish and stop control system task for simulation exit or pause
08:16 Advantage of dataflow over gate-level modeling for sequential circuits flip-flop
09:23 How to code SR flip flop using verilog dataflow modeling style
11:29 SR FlipFlop module
13:36 CORRECTION: When it comes to syntax, the difference between DataFlow Modeling and Behavioral Modeling is the use of assign keyword. I forgot to forcibly use the assign keyword. But the latest version of Verilog is intelligent enough to make it work.
20:43 How to create clock pulses using forever keyword and delay

[@jsbadhon]

Hi, great tutorial but I have a question. Can you please tell me why after 20ns qb is not immediately rises to 1 ?(though q is immediately falls to 0). I can see from the graph qb appends to 1 after 1 clock cycle after the 20 ns. Why is that?

[@boyfriendnibluefairy]

I think it has something to do with QB waiting for the output coming from Q before it toggles its value (see timestamp 09:00)