Question : Stian is your customer and he wants to buy an UART receiver (UART-RX) with following parameters: the baud rate of 38.4 kbps, even parity bit, one-stop bits, 5 data bits and 32-time oversampling technique. Below steps you should follow to complete your UART-RX design in FPGA for Stian’s order (a) You decide to use mod-m-counter to interface between the UART-RX and the clock source on NEXYS-4 board (fclk = 100MHz). What are the values of N,M used to generate the tick signal for UART-RX? (b) Write the component declaration and instantiation for such mod-m-counter. (c) Write the boolean equation to calculate the odd parity bit. (d) Define the finite state machine of the UART-Rx in VHDL (e) Write VHDL codes for the sequential part of the UART-RX finite state machine. (f) Write VHDL codes for the combinational part of the UART-RX finite state machine. Note: Fully present the transitional conditions among states can you slov this question thanks
u said the mod 10 counter wrong at last...if we use one nand for the two 1s then it will be a mod 9 counter...bcoz 9 also has two 1s at that very place....
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Nice madam but we can explain the clock cycle also it's more useful for us
Thankyou so much...finally after completing my btech today i understood how counters works
Sir, how many D flip flops we have to use in order to build n a divide by n counters, thanks
Question : Stian is your customer and he wants to buy an UART receiver (UART-RX) with following parameters: the baud rate of 38.4 kbps, even parity bit, one-stop bits, 5 data bits and 32-time oversampling technique. Below steps you should follow to complete your UART-RX design in FPGA for Stian’s order
(a) You decide to use mod-m-counter to interface between the UART-RX and the clock source on NEXYS-4 board (fclk = 100MHz). What are the values of N,M used to generate the tick signal for UART-RX?
(b) Write the component declaration and instantiation for such mod-m-counter.
(c) Write the boolean equation to calculate the odd parity bit.
(d) Define the finite state machine of the UART-Rx in VHDL
(e) Write VHDL codes for the sequential part of the UART-RX finite state machine.
(f) Write VHDL codes for the combinational part of the UART-RX finite state machine. Note: Fully present the transitional conditions among states
can you slov this question
thanks
This was SO helpful. Thank you!
Amazing, best digital electronics lecturer on youtube!
Mam, how we can know that given circuit is +ve or -ve edge trigger ?????
ma'am u are GREAT .THANKS A LOT .
THANK you so much mam.....very Nice explanation
Brilliant explanation mam u such do hard work keep it up
Bro most of her video are wrong
how to now active low or high preset and clear input? what the different betweet that?
How do you modify this to make a mod-24 counter? I need it for a digital watch project.
You would need a chip with 5 counters in it, and your resets would need to be set to QD and QE.
I want RVSP lectures can you do?
Awesome video , thank you ma'am
you are the best,ma'am!!!!!
Thank you so much mam . very nice explanation
Thank you very much. However, I had a question, how about the mod 15 counter
Thankyou Mam for improving nd increasing my concepts.👍🙏
madam ,you have to connect all q1 q2 q 3 q4 to nand gate other wise it will clear the o/p s even 00(00) ,10(00), 1100[only that need to clear]
very good tutotorial to help my exam
U are brilliant mam👍👍👍
u said the mod 10 counter wrong at last...if we use one nand for the two 1s then it will be a mod 9 counter...bcoz 9 also has two 1s at that very place....
How many flipflop are required in mod 22 iska kya answer hai ????
Thx so much
If we connect 7 segment with decoder it count from 0 to 11
Or from 0 to 12
Then reset
I think it reset after count from 0 to 11
Preset
Mam,I think in 12 clock pulse it will reset as 0000
You've done it in next stage.
Yes
well explained thanks mam
This videos are Claer And very interesting videos but please do THIS VIDEO USING SR,JKand DFlipFlop
Thank You!
What is the maximum counting state 11 or 12
Counting will be 0-11 or 1-12
veera venky but 0 means no clock pulse
Vidu Sharm
For mod-12
N>=2n
12>=2^4
12>=16
Vidu Sharma
Mod-12 we can reset at 12 count (1101)
Or mod-10 we can reset at 10 count means 1010.
Counter will start counting from 0
It will be 12.....0 to 11
Amazing vdeos
12-mod counter mean 0-11 count but why you are count till 12 ?
omg, thank you so much for this video! I understood completely well
Nice explained
What to do when the counter is positive edge triggered?
Nachoo 😁
Nice mem.👌👌👌
How to design mod-12 asynchronous up counter using active clear high input.
Just q3 and q2 connect to AND gate then u will get 1 as y then 1 acts as active high
Thank you.
Thanks 😊
Mam but mod 12 means we have to take the states upto 11 mam...??that means 0 to 11
Yes, it is counting from 0-11. As soon as 12 (1100) is encountered states are cleared (there is nand gate for it). Hope it helps.
Thank you mam
Thanku mam
Tysm mam
English me padhana jaruri hota hai kya?
I need you explain an exercise
thankyou
Mod 150 how to make
♥️
Thanks ;-) ;-)
hai ca am fentat restanta ms
Madam rvsp lecture pls
Designmod 15 Asynchronous Counte
Mam is this 12 counter???? I think it is 13 counter.
nope
❤️❤️❤️❤️❤️
Design a series Counters satisfy a mod - 12 ??
اليعرف يحله خلي يرد بليز
you r the best~~🤗🤗🤗
Mam
What is decade counter?
Shiva Kumar it'll count to 10
Count from 0 to9
Mod 10 counter using jkflipflop
mod-9 aur mod-32 aaj kardejiye plzzz
Cine s-o fi gandit ca imi trebuiesc astea la faculta :-s :-s
Smjhana hi nahi aata
Thanks ;-) ;-)
mod-9 aur mod-32 aaj kardejiye plzzz