UVM Reporting | UVM S2

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  • Опубликовано: 25 дек 2024
  • This is the Second video in the series UVM Tutorial. This video is about the UVM Reporting
    UVM Reporting or Messaging has a rich set of message-display commands & methods to alter the numbers & types of messages that are displayed without re-compilation of the design. UVM Reporting also includes the ability to mask or change the severity of the message to adapt the required environment condition.
    UVM Reporting has the concepts of Severity, Verbosity and Simulation Handing Behavior. Each of them can be independently specified and controlled. Now lets see what each of these indicates:
    Severity:
    Severity indicates importance
    Examples are Fatal, Error, Warning & Info
    Verbosity:
    Verbosity indicates filter level
    Examples are None, Low, Medium, High, Full & Debug
    Simulation Handling Behavior:
    This controls simulator behavior
    Examples are Exit, Count, Display, Log, Call Hook & No Action
    #UVM - Universal Verification Methodology is a standardized #methodology for verifying integrated circuit designs. It is a must for #VLSI engineers to understand.
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Комментарии • 15

  • @jyotiprasadkurmi2363
    @jyotiprasadkurmi2363 2 года назад

    This videos are actually helping me a lot. Thank you

    • @vlsichaps
      @vlsichaps  2 года назад

      Glad to know that.

    • @vlsichaps
      @vlsichaps  2 года назад

      Keep supporting our mission in possible ways.

  • @mahaveerchougala4907
    @mahaveerchougala4907 2 года назад +2

    Sir All videos on SV are really good and useful and also Please do upload more videos on UVM

  • @guvvalavenkatesh7849
    @guvvalavenkatesh7849 2 года назад +1

    Please do more videos regarding this. its useful for us

  • @sivalankalaanitha3022
    @sivalankalaanitha3022 2 года назад +1

    Pls upload more video on uvm

  • @saisrikanth378
    @saisrikanth378 2 года назад

    Continue this playlist further with all the uvm topics

  • @keerthianil680
    @keerthianil680 2 года назад +1

    sir your explanation is good .can u please do more videos on UVM topics like phases,factory,utility & field macros,virtual sequence and virtual sequencer ,tlm ports

  • @gurushantshivankar3008
    @gurushantshivankar3008 2 года назад +1

    please make more videos on more uvm topics

  • @rutvikmakwana2191
    @rutvikmakwana2191 2 года назад +1

    Sir when uploading more video on UVM?

  • @suchitrajaee8379
    @suchitrajaee8379 2 года назад

    Sir can you make next video on TLM ports