System Verilog Tut 18 | Functional Coverage | Implicit Bins

[@thatguy6442]

You are a gem

[@akshayshah000]

So good, Come up with more sir. Thank you..

[@devanshumaheshwari8301]

Yeah... really good, when can we expect further videos for functional coverage!

[@akkammakoti8981]

Very nice video

[@placement3608]

Superb.

[@PrabhatKumar-zk8sp]

very good ,please add more videos and coverage topics video

[@vlsichaps]

Sure.

[@vlsichaps]

Soon.

[@hukmur3712]

Impatient for explicit bins

[@mughahotoyeptho1615]

Very nice lecture.. please upload the content more topics on SV and UVM

[@eslammorsie4908]

Thanks for the video, I have a question I am using VCS simulator and I want to know how to see the report in time 9:43 of the video?

[@RAHULPATEL-id9cv]

why do we use rand in place of randc which provide better coverage?

[@mathema5153]

In latest eda mentor questa is not showing?? Whenever I am trying siemens questa nothing is happening

[@Saikiran-ze1dx]

sir , when will you upload assertions topic ??

[@reguideu2266]

What happens if you put randc instead of rand?

[@landachandu5770]

Please do more videos sir

[@vlsichaps]

Sure..!!

[@bishalghoshb3412]

plz upload more video

[@vlsichaps]

Sure Dear, Next video is getting uploaded in a few minutes.
Can you guess the title? :-)

[@RahulGupta-rw6sd]

Sir please upload more videos.