Very nicely explained..👏.I have one doubt ,you told that instance override is only applicable to components and it is not applicable to uvm_transaction,uvm_sequence etc as component consists of hierarchy but uvm_transaction,uvm_sequence don't have this hierarchy.Could you please explain how the above doesn't have any hierarchy.As I am new to this Uvm.so I need to know this.
It comes down to the diff between uvm components (drivers, scb, monitors, etc.) and uvm objects (transactions, seq items, etc). Uvm transaction / seq items are dynamic , transients and as thus their constructors only has name as an arguments whereas, components are static and exist throughout the simulation and their constructor has both name and hierarchy.
Thank you! Very clear to me.
Nicely explained
Keep watching
Thank you, very useful
Glad it was helpful!
Very nicely explained..👏.I have one doubt ,you told that instance override
is only applicable to components and it is not applicable to uvm_transaction,uvm_sequence etc as component consists of hierarchy
but uvm_transaction,uvm_sequence don't have this hierarchy.Could you please explain how the above doesn't have any hierarchy.As I am new to this Uvm.so I need to know this.
It comes down to the diff between uvm components (drivers, scb, monitors, etc.) and uvm objects (transactions, seq items, etc). Uvm transaction / seq items are dynamic , transients and as thus their constructors only has name as an arguments whereas, components are static and exist throughout the simulation and their constructor has both name and hierarchy.
Can you do a video on - how to verify a memory in UVM/system verilog ? what are the things we need to test for memory and then how ?
Hi Palli,
I will add it to my list and create a video on it.
Thanks
Nathan Junction
Stehr Bypass
Doyle Alley
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