virtual sequence & virtual sequencer w.r.p.t system Verilog UVM.

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  • Опубликовано: 26 дек 2024

Комментарии • 25

  • @kirtikansal6946
    @kirtikansal6946 Год назад +5

    kudos to the energy that you put in explaining the toughest topic, relating the codes and the diagrams, making the learners more enthusiastic to grasp more..
    appreciable efforts.

  • @easytunesparks1317
    @easytunesparks1317 2 года назад +3

    Informative... Thanks for adding the video...

  • @ganeshpatil7199
    @ganeshpatil7199 3 месяца назад +1

    Next level explanation...
    Thank you so much...The explanation is exactly what I was looking for (industry specific)👏🙌😊

  • @MunsifMAhmad
    @MunsifMAhmad  2 года назад +4

    Small correction @6:19 ..
    Virtual sequencer is a component class in the UVM base class hierarchy, hence it's default constructor has 2 arguments..
    @8:58 -> difference between object and component classes.

  • @bestenglishlearning5049
    @bestenglishlearning5049 Год назад +1

    So good in explanation. Good luck Sir.

  • @mayankyadav2720
    @mayankyadav2720 2 года назад +1

    Very good explanation sir , keep on covering topics sir. Very helpful for us. Keep the good work up ! ❤️

  • @j_______patil2920
    @j_______patil2920 2 года назад +1

    Tqs for explanation 😃😊

  • @AbijithP-y1f
    @AbijithP-y1f 9 месяцев назад

    great job

  • @ichus0098
    @ichus0098 Год назад +1

    What is the use of `uvm_do_on macro and 'uvm_declare_p_sequencer() in UVM virtual sequence ?

    • @MunsifMAhmad
      @MunsifMAhmad  Год назад

      `uvm_do_on
      This is the same as `uvm_do except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified SEQR argument.
      Reference:-
      verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files/macros/uvm_sequence_defines-svh.html#:~:text=%60uvm_do_on,-%60uvm_do_on(SEQ_OR_ITEM%2C&text=This%20is%20the%20same%20as%20%60uvm_do%20except%20that%20it%20also,to%20the%20specified%20SEQR%20argument.
      This macro is used to declare a variable p_sequencer whose type is specified by SEQUENCER.
      Reference:-
      verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files/macros/uvm_sequence_defines-svh.html#%60uvm_declare_p_sequencer

  • @rasagnasaranga1405
    @rasagnasaranga1405 2 года назад +1

    Sir explain all the uvm and also have any material please share

    • @MunsifMAhmad
      @MunsifMAhmad  2 года назад +1

      Yes i will try, U can use verification guide, verification academy and UVM Cook Book as a reference..

    • @bhadrappavadageri1818
      @bhadrappavadageri1818 2 года назад

      @@MunsifMAhmad please explain all UVM concepts

    • @MunsifMAhmad
      @MunsifMAhmad  2 года назад

      @@bhadrappavadageri1818 will try if possible..

  • @Lucky-ks5hz
    @Lucky-ks5hz 2 года назад +1

    Sir Who will write virtual seq and virtual seqr. Testcase writer or tb developer.!

  • @tnaveenlatha
    @tnaveenlatha 2 года назад +1

    Hi,
    Can you please explain with two agents..

    • @MunsifMAhmad
      @MunsifMAhmad  2 года назад +1

      Will upload a video soon:)

    • @MunsifMAhmad
      @MunsifMAhmad  Год назад +1

      You will find two agents in implementation video:)

  • @writetorohit
    @writetorohit Год назад +1

    Is it mandatory to pass parameters to sequence, sequencer,driver classes ?

    • @MunsifMAhmad
      @MunsifMAhmad  Год назад +1

      Yes.. u can understand it better if look at the handshaking mechanisms between driver and sequence, where sequencer work as a mediator..

  • @shubhampandey7275
    @shubhampandey7275 Год назад

    But here also, in case of multiple agents with seqr, testcase writter gets dependent on testbench writter to know the number of such agents with seqr...
    Then how is this clearing their dependency??

    • @UVLS
      @UVLS Год назад

      Instead of knowing the entire hierarchy to the agent sequencer , the testcase developer will just get details of virtual sequencer from the testbench developer . which helps testcase developer to develop complex scenarios .