Munsif M. Ahmad
Munsif M. Ahmad
  • Видео 112
  • Просмотров 288 158
Verilog FAQ's, verilog code for posedge detector & implementation of latch using 2x1 mux.
This video is all about how to write verilog code for posedge detector & how to implementation of latch using 2x1 mux.
EDA Playground link:- edaplayground.com/x/Zqsj
Digital electronics FAQ's Playlist:- ruclips.net/p/PLDAnhhk0KczzR5FYjRgiJ4PZgCJcMmc_p
Verilog FAQ's Playlist:- ruclips.net/p/PLDAnhhk0Kczy_KV4L_i9oiNTDzF7NQNWv
#semiconductor #vlsi #verilog #faq #interviewquestion #electronicengineering #veriloghdl #multiplexer #latch #posedgedetector
Просмотров: 302

Видео

Verilog FAQ's, clock generation in Verilog, abstraction levels, full adder using 2 half adder.24:37Verilog FAQ's, clock generation in Verilog, abstraction levels, full adder using 2 half adder.
Verilog FAQ's, clock generation in Verilog, abstraction levels, full adder using 2 half adder.
Просмотров 28910 месяцев назад
This video is all about Verilog HDL FAQ's // Q1) 5 different way's to generate clock in Verilog ? // Q2) Explain different abstraction levels, Implement full adder using 2 half adder ? EDA Playground link:- edaplayground.com/x/mtEY Verilog FAQ's Playlist:- ruclips.net/p/PLDAnhhk0Kczy_KV4L_i9oiNTDzF7NQNWv Digital Electronics Playlist:- ruclips.net/p/PLDAnhhk0KczzR5FYjRgiJ4PZgCJcMmc_p #semiconduc...
Repetition Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #0718:42Repetition Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #07
Repetition Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #07
Просмотров 2,8 тыс.Год назад
This video is all about the introduction to Repetition Operators (Consecutive & Non-Consecutive) with respect to SVA (System Verilog Assertions). EDA Playground Link:- edaplayground.com/x/DxVG #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA #RepetitionOperators
Timing Windows w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #0614:51Timing Windows w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #06
Timing Windows w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #06
Просмотров 2,6 тыс.Год назад
This video is all about the introduction to Timing Windows with respect to SVA (System Verilog Assertions). EDA Playground Link:- www.edaplayground.com/x/Fsyc #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA #svatimingwindows
Implication Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #0520:17Implication Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #05
Implication Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #05
Просмотров 3,2 тыс.Год назад
This video is all about the introduction to Implication Operators with respect to SVA (System Verilog Assertions). EDA Playground Link:- www.edaplayground.com/x/YsEf #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA
Building blocks of SVA (System Verilog Assertions) SVA VIDEO #0420:00Building blocks of SVA (System Verilog Assertions) SVA VIDEO #04
Building blocks of SVA (System Verilog Assertions) SVA VIDEO #04
Просмотров 4 тыс.Год назад
This video is all about the introduction to Building blocks with respect to SVA (System Verilog Assertions). #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA
Built-in System Function in SVA (System Verilog Assertions) SVA VIDEO #0330:16Built-in System Function in SVA (System Verilog Assertions) SVA VIDEO #03
Built-in System Function in SVA (System Verilog Assertions) SVA VIDEO #03
Просмотров 6 тыс.Год назад
This video is all about the introduction to Built-in System Functions with respect to SVA (System Verilog Assertions). EDA Playground Link For $rose system function: www.edaplayground.com/x/LfTL #verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA
Concept of call-backs w.r.p.t sv-uvm (System Verilog Version of UVM) Part-2 (Modified)17:16Concept of call-backs w.r.p.t sv-uvm (System Verilog Version of UVM) Part-2 (Modified)
Concept of call-backs w.r.p.t sv-uvm (System Verilog Version of UVM) Part-2 (Modified)
Просмотров 1,5 тыс.Год назад
This video is all about the concept of call-backs w.r.p.t System Verilog Version of UVM (Universal Verification Methodology) with a very simple example. Combinational adder verification using sv-uvm:- ruclips.net/video/blAiR11Xv8k/видео.html EDA Playground Link:- edaplayground.com/x/wPQn #semiconductor #vlsi #uvm #uvm4verfication #svuvm #callbacks #vlsifaq #froentenddesignandverification #elect...
Concept of memory declaration in RAL w.r.p.t System Verilog Version of UVM -- SV-UVM RAL VIDEO #1712:49Concept of memory declaration in RAL w.r.p.t System Verilog Version of UVM -- SV-UVM RAL VIDEO #17
Concept of memory declaration in RAL w.r.p.t System Verilog Version of UVM -- SV-UVM RAL VIDEO #17
Просмотров 1,7 тыс.Год назад
This video is all about the concept of memory class declaration w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define mem class , how to define predictor & scoreboard classes in the environment , how to connect monitor analysis port with analysis implementation ports of predictor & scoreboard, for the DUT which has a single m...
Example of functional coverage for register w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #1616:25Example of functional coverage for register w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #16
Example of functional coverage for register w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #16
Просмотров 2,4 тыс.Год назад
This video is all about the concept of functional coverage for register with example w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define coverage for register, how to define predictor in the environment class, how to connect monitor and predictor, for the DUT which has a single register in it, with single field F0. EDA Play...
Example for explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #1521:01Example for explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #15
Example for explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #15
Просмотров 1,6 тыс.Год назад
This video is all about the concept of explicit prediction example w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define predictor in the environment class, how to connect monitor and predictor for the DUT which has a single register in it, with single field F0. EDA Playground link:- edaplayground.com/x/WTn8 Explicit predicti...
Explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #1415:03Explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #14
Explicit prediction w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #14
Просмотров 1,4 тыс.Год назад
This video is all about the concept of explicit prediction w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer), How to define predictor in the environment class, how to connect monitor and predictor for the DUT which has a single register in it, with single field F0. #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #se...
reset method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #1311:47reset method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #13
reset method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #13
Просмотров 1,1 тыс.Год назад
This video is all about the concept of reset method w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer). EDA Playground Link:- edaplayground.com/x/Unw7 #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #semiconductor #ral #uvm4verification #register_abstraction_layer #registersequence #uvmral #RAL
randomize method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #128:00randomize method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #12
randomize method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #12
Просмотров 1,1 тыс.Год назад
This video is all about the concept of randomize method w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer). EDA Playground Link:- edaplayground.com/x/8na7 #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #semiconductor #ral #uvm4verification #register_abstraction_layer #registersequence #uvmral #RAL
Update method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #119:06Update method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #11
Update method w.r.p.t SV-UVM RAL -- SV-UVM RAL VIDEO #11
Просмотров 1,2 тыс.Год назад
This video is all about the concept of update method w.r.p.t SV-UVM RAL (System Verilog version of Universal Verification Methodology Register Abstraction Layer). EDA Playground Link:- edaplayground.com/x/GBwe #uvm #verification #vlsi #electronicengineer #faq #interviewquestion #semiconductor #ral #uvm4verification #register_abstraction_layer #registersequence #uvmral #RAL
Mirror method w.r.p.t SV-UVM RAL - SV-UVM RAL VIDEO #1016:09Mirror method w.r.p.t SV-UVM RAL - SV-UVM RAL VIDEO #10
Mirror method w.r.p.t SV-UVM RAL - SV-UVM RAL VIDEO #10
Просмотров 1,9 тыс.Год назад
Mirror method w.r.p.t SV-UVM RAL - SV-UVM RAL VIDEO #10
Predict method in SV-UVM RAL (Register Abstraction Layer) SV-UVM RAL VIDEO #099:02Predict method in SV-UVM RAL (Register Abstraction Layer) SV-UVM RAL VIDEO #09
Predict method in SV-UVM RAL (Register Abstraction Layer) SV-UVM RAL VIDEO #09
Просмотров 2,5 тыс.Год назад
Predict method in SV-UVM RAL (Register Abstraction Layer) SV-UVM RAL VIDEO #09
front door write, read methods & backdoor poke, peek methods SV-UVM RAL VIDEO #0821:45front door write, read methods & backdoor poke, peek methods SV-UVM RAL VIDEO #08
front door write, read methods & backdoor poke, peek methods SV-UVM RAL VIDEO #08
Просмотров 4 тыс.Год назад
front door write, read methods & backdoor poke, peek methods SV-UVM RAL VIDEO #08
set, get, get_mirrored_value, and write methods in RAL SV-UVM RAL VIDEO #0718:22set, get, get_mirrored_value, and write methods in RAL SV-UVM RAL VIDEO #07
set, get, get_mirrored_value, and write methods in RAL SV-UVM RAL VIDEO #07
Просмотров 3,5 тыс.Год назад
set, get, get_mirrored_value, and write methods in RAL SV-UVM RAL VIDEO #07
Transaction, Agent, and Register sequence classes - SV-UVM RAL VIDEO #0615:11Transaction, Agent, and Register sequence classes - SV-UVM RAL VIDEO #06
Transaction, Agent, and Register sequence classes - SV-UVM RAL VIDEO #06
Просмотров 3,2 тыс.Год назад
Transaction, Agent, and Register sequence classes - SV-UVM RAL VIDEO #06
Concept of an adapter in RAL w.r.p.t System Verilog Version of UVM - SV-UVM RAL VIDEO #0515:07Concept of an adapter in RAL w.r.p.t System Verilog Version of UVM - SV-UVM RAL VIDEO #05
Concept of an adapter in RAL w.r.p.t System Verilog Version of UVM - SV-UVM RAL VIDEO #05
Просмотров 4,8 тыс.Год назад
Concept of an adapter in RAL w.r.p.t System Verilog Version of UVM - SV-UVM RAL VIDEO #05
Register Abstraction Layer (RAL) SV-UVM RAL VIDEO #0426:08Register Abstraction Layer (RAL) SV-UVM RAL VIDEO #04
Register Abstraction Layer (RAL) SV-UVM RAL VIDEO #04
Просмотров 14 тыс.Год назад
Register Abstraction Layer (RAL) SV-UVM RAL VIDEO #04
Concept of call-backs w.r.p.t sv-uvm15:15Concept of call-backs w.r.p.t sv-uvm
Concept of call-backs w.r.p.t sv-uvm
Просмотров 3 тыс.Год назад
Concept of call-backs w.r.p.t sv-uvm
Array sorting methods w.r.p.t System Verilog5:41Array sorting methods w.r.p.t System Verilog
Array sorting methods w.r.p.t System Verilog
Просмотров 957Год назад
Array sorting methods w.r.p.t System Verilog
Can we implement a NOT gate using AND gate?13:40Can we implement a NOT gate using AND gate?
Can we implement a NOT gate using AND gate?
Просмотров 418Год назад
Can we implement a NOT gate using AND gate?
Objection mechanism w.r.p.t System Verilog version of UVM11:41Objection mechanism w.r.p.t System Verilog version of UVM
Objection mechanism w.r.p.t System Verilog version of UVM
Просмотров 2,5 тыс.Год назад
Objection mechanism w.r.p.t System Verilog version of UVM
Design & verification of Protocols using sv-hdl & sv-uvm4:04Design & verification of Protocols using sv-hdl & sv-uvm
Design & verification of Protocols using sv-hdl & sv-uvm
Просмотров 1,1 тыс.Год назад
Design & verification of Protocols using sv-hdl & sv-uvm
Blocking communication w.r.p.t cocotb12:28Blocking communication w.r.p.t cocotb
Blocking communication w.r.p.t cocotb
Просмотров 477Год назад
Blocking communication w.r.p.t cocotb
uvm_subscriber w.r.p.t sv-uvm "FC VIDEO #12"15:01uvm_subscriber w.r.p.t sv-uvm "FC VIDEO #12"
uvm_subscriber w.r.p.t sv-uvm "FC VIDEO #12"
Просмотров 2,3 тыс.Год назад
uvm_subscriber w.r.p.t sv-uvm "FC VIDEO #12"
Full adder coverage model using System Verilog (Linear TB) "FC VIDEO #11"6:08Full adder coverage model using System Verilog (Linear TB) "FC VIDEO #11"
Full adder coverage model using System Verilog (Linear TB) "FC VIDEO #11"
Просмотров 2,2 тыс.Год назад
Full adder coverage model using System Verilog (Linear TB) "FC VIDEO #11"

Комментарии

  • @madeeasy...5976
    @madeeasy...5976 День назад

    voice is not louder

  • @DVSSubramanyaPraneethTurubati
    @DVSSubramanyaPraneethTurubati 3 дня назад

    Wonderful explanation that made me love this functional coverage. Thanks bhai

  • @ranjanapatige1204
    @ranjanapatige1204 14 дней назад

    Please complete the series upto SVA Control tasks... plss sir it will be very much helpful for us...

    • @MunsifMAhmad
      @MunsifMAhmad 10 дней назад

      Will upload new concepts soon..

  • @kaverih6611
    @kaverih6611 15 дней назад

    Thank you its more helpful🙌

  • @nagasindhuchimakurthy7012
    @nagasindhuchimakurthy7012 15 дней назад

    A small request from my end.. could you please explain the event scheduler in system verilog in detail?

  • @BigEndian43
    @BigEndian43 15 дней назад

    Do you maybe know the reason why the register model can be null inside the register sequence?

  • @bvkmohan6732
    @bvkmohan6732 23 дня назад

    Showing one error

  • @shyamgudikandula3877
    @shyamgudikandula3877 25 дней назад

    Sir, can you please explain of how to execute these waveforms with all those flags

  • @JADHAVKAUSHAL
    @JADHAVKAUSHAL 26 дней назад

    sir while ruuning the code i didnt get that table can you help ?

  • @balasubramanianr2238
    @balasubramanianr2238 Месяц назад

    Thanks for sharing the information

  • @shaikshareef4583
    @shaikshareef4583 Месяц назад

    Nice video

  • @Jumptrix
    @Jumptrix Месяц назад

    What is Static and Dynamic bins ? It was an interview question asked to me ? Can you explain what it is ? the interviewer told it is not implicit and explicit bins ? Can you give me a practical example for it ? I found this as a answer is it correct bins b1 = [0:7];//static bins bins b1 = ![0:7]; //dynamic bins

    • @MunsifMAhmad
      @MunsifMAhmad Месяц назад

      @@Jumptrix i will chek and share..

  • @RandomHubbb
    @RandomHubbb Месяц назад

    what happened to the go to operator video? lol

  • @RandomHubbb
    @RandomHubbb Месяц назад

    => ##1 a ##1 is confusing. it feels like a may not be high after the clock cycle when we see the blue box, but a cycle later. shouldnt it say -> instead of =>?

  • @Jumptrix
    @Jumptrix Месяц назад

    why we are passing uvm_sequence_item as a parameter for the virtual sequencer ?

  • @RandomHubbb
    @RandomHubbb Месяц назад

    you are amazing! way to demystify SVAs!

  • @zezozezo5103
    @zezozezo5103 Месяц назад

    Very helpfull

  • @zezozezo5103
    @zezozezo5103 Месяц назад

    Your the best thank you

  • @MyINDIANway-yx1om
    @MyINDIANway-yx1om Месяц назад

    How this activecount is displayed in waveform

    • @MunsifMAhmad
      @MunsifMAhmad Месяц назад

      @@MyINDIANway-yx1om in view tab, you will see assertion add this to waveform..

    • @MyINDIANway-yx1om
      @MyINDIANway-yx1om Месяц назад

      Can you send me your linkedin I'd.. I want to ask you some questions

    • @MyINDIANway-yx1om
      @MyINDIANway-yx1om Месяц назад

      @@MunsifMAhmad do you know why active count font increase

  • @uma_k_k
    @uma_k_k 2 месяца назад

    pls explain about pack/unpack, record and other methods also

  • @MyINDIANway-yx1om
    @MyINDIANway-yx1om 2 месяца назад

    How to get assertions report

  • @lucianosaldivia5917
    @lucianosaldivia5917 2 месяца назад

    saying that something is very simple every 20 seconds and just reading what's beign shown is not explaining and it does NOT make things any simpler

  • @Jumptrix
    @Jumptrix 2 месяца назад

    Your Explanations are very clear😇💥.It's easy to grasp the concepts quickly .

  • @pavanitamma5917
    @pavanitamma5917 2 месяца назад

    Thank you for SVA series 🤩really helpful

  • @SaikiranReddy-c8p
    @SaikiranReddy-c8p 2 месяца назад

    both bins functionallity is same the main difference is that generating or showing error msg in the simulator.if we donot want to see where errors occured we use ignore otherwise we use illegeal bins

  • @ngocmanprocoder
    @ngocmanprocoder 2 месяца назад

    I have used virtual sequence and I have given the warning "No default phase sequence for phase 'run'" as running. How is this case? I have no idea whether it can cause any deep issues for my program or not. Many thanks.

  • @AshokNaik_20
    @AshokNaik_20 3 месяца назад

    Great expectation for virtual sequence and sequencer

  • @PrashanthsVlog
    @PrashanthsVlog 3 месяца назад

    Please don't stop teaching vlsi concept specially sv and uvm

  • @qeq167
    @qeq167 3 месяца назад

    this is wonderful, finally i can understand functional coverage

  • @kapavarapumadhuri
    @kapavarapumadhuri 3 месяца назад

    Amazing Explanation. If possible can you please share the presentation.

  • @trashbin-u1h
    @trashbin-u1h 3 месяца назад

    HI, Can you share the EDA Link for the example you are showing above?? Also, thank you for such a detailed explanation of RAL.

    • @MunsifMAhmad
      @MunsifMAhmad 3 месяца назад

      @@trashbin-u1h Link is alredy there in the description ..

    • @trashbin-u1h
      @trashbin-u1h 3 месяца назад

      @@MunsifMAhmad Got it, Thank You

    • @trashbin-u1h
      @trashbin-u1h 3 месяца назад

      I am also looking for uvm_reg_callback tutorials. Please suggest.

  • @hossamfadeel
    @hossamfadeel 3 месяца назад

    Appreciate your efforts.

  • @hossamfadeel
    @hossamfadeel 3 месяца назад

    Appreciate your efforts.

  • @ngocmanprocoder
    @ngocmanprocoder 3 месяца назад

    Which class does the functional coverage class extend if I write this in UVM testbench? (maybe uvm_subscriber?) Many thanks.

  • @PrashanthsVlog
    @PrashanthsVlog 3 месяца назад

    Uvm?

  • @ganeshpatil7199
    @ganeshpatil7199 3 месяца назад

    Next level explanation... Thank you so much...The explanation is exactly what I was looking for (industry specific)👏🙌😊

  • @agame1239
    @agame1239 3 месяца назад

    When i click view there is no schematic option for me The options i got are less than your options

  • @EdwardRobinson-c6n
    @EdwardRobinson-c6n 3 месяца назад

    1613 Sasha Keys

  • @uday7777777
    @uday7777777 4 месяца назад

    Amazing ...Thanks for an excellent explaination.

  • @jinayshah9134
    @jinayshah9134 4 месяца назад

    pls suggest what to do when we have multiple monitors and one subscriber class

  • @NATUKODI_FIT_BOY
    @NATUKODI_FIT_BOY 4 месяца назад

    can you post the code and all that will maek us to explore the code on our own and get some good experience

    • @MunsifMAhmad
      @MunsifMAhmad 4 месяца назад

      Hi .. Already EDA playground link is there in the description section, pls have a look..

  • @prafullgaupale9713
    @prafullgaupale9713 4 месяца назад

    I watched all videos in single go ...it is Very informative and gives easy understanding of RAL....like others I am also waiting for next videos ...Thanks for RAL videos ...

  • @prafullgaupale9713
    @prafullgaupale9713 4 месяца назад

    we just driven wr_enb as 1 when write...and then how wr_enb got 0 and output came onto dout i did not understood ....

  • @vishalgowtham896
    @vishalgowtham896 4 месяца назад

    easy to understand and need more videos on UVM , THANK YOU AHMAD

  • @utkarshraj9064
    @utkarshraj9064 4 месяца назад

    jab b mai kuch badhiya content pata hun yt pr, kuch na kuch issue rehti hi hai, munsif bhai.....mic to recheck kr lete bhai...bahut sahi content hai, par clear sunai de tabto

  • @shaikfaheed7353
    @shaikfaheed7353 4 месяца назад

    Thanks u for explaining briefly

  • @uditgohil7547
    @uditgohil7547 4 месяца назад

    Indeep explanation with comments good job sir ji

  • @vishalgowtham896
    @vishalgowtham896 4 месяца назад

    very useful and easily explained . Than you Ahmed sir, one doubt ---Is phases are written for every component ??

  • @harineerathod4506
    @harineerathod4506 4 месяца назад

    Thank you so much, very clear and informative video

  • @pratyushpathak9052
    @pratyushpathak9052 4 месяца назад

    Please do something about audio quality.