Objection mechanism w.r.p.t System Verilog version of UVM

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  • Опубликовано: 27 дек 2024

Комментарии • 5

  • @NC-eu8dp
    @NC-eu8dp 5 месяцев назад

    Hi! nice video. A question i have a UVM project, and one test called Testcase05 that never finish. How i can use +UVM_OBJECTION_TRACE in vsim directive if it no finish? Because the TRACE OBJECTION is in transcript when it finish...

  • @rishijain7988
    @rishijain7988 Год назад +1

    thanks

  • @ajay5381
    @ajay5381 Год назад

    Sir aap bol rhe thae... Protocol iss week aayega

    • @MunsifMAhmad
      @MunsifMAhmad  Год назад +2

      Hi Ajay..
      Sorry for the delay, due to time constraints not able to complete it, but soon will upload protocol videos..

    • @ajay5381
      @ajay5381 Год назад

      @@MunsifMAhmad oky sir