Built-in System Function in SVA (System Verilog Assertions) SVA VIDEO #03

[@hossamfadeel]

Appreciate your efforts.

[@MANISHKUMAR-ee2ty]

Good explanation...
Thank you so much for this SVA lecture series...

[@MunsifMAhmad]

So nice of you..

[@NARASIMHARAORAGHAVA]

it's very help full I like your teaching and way of explanation ..tq u so much...🤝

[@MunsifMAhmad]

Thanks.. 😊

[@shreedharaks6416]

Very informative. Appreciate your effort to make it

[@Wander_freak]

very helpful

[@uday7777777]

Thank you so much. It helped me a lot

[@ichus0098]

Bro please upload the next part ASAP.

[@MunsifMAhmad]

Soon will upload more SVA videos..

[@MyINDIANway-yx1om]

How this activecount is displayed in waveform

[@MunsifMAhmad]

@@MyINDIANway-yx1om in view tab, you will see assertion add this to waveform..

[@MyINDIANway-yx1om]

Can you send me your linkedin I'd.. I want to ask you some questions

[@MyINDIANway-yx1om]

@@MunsifMAhmad do you know why active count font increase

[@madhumohan5605]

sir upload the notes

[@MunsifMAhmad]

Pls share ur mail ID..

[@Shahidsoc]

upload slides brother, ✌