Assertion Introduction SVA VIDEO #02

This video is all about the introduction to SVA(System Verilog Assertions, What are assertions, Why to use assertions, Who will write the assertions, some advantages, and limitations of assertions.
#verification #semiconductor #vlsi #systemverilog #systemverilog4verificatio #faq #interviewquestion #electronicengineering #verification #assertions #sva #powerofaseertions #SVA

[@MunsifMAhmad]

Small correction @1:20 It is a verification technique that is embedded in the language (SV).

[@amitkumarpaswan2251]

nice and very good explanation.

[@gvenkatesh6671]

please do more videos Ahmad.....!!! Tnx for your effort gbu

[@shashvatmaurya6791]

gbu?

[@PrabhatKumar-zk8sp]

please add more videos on assertion. Your explantion is very good and easy to understand

[@MunsifMAhmad]

Soon will upload more videos..

[@shreedharaks6416]

Very nicely Explained

[@VinayKumar-ud5hr]

Please make more videos on assertions it will useful for us
When was the nxt video on assertions....?

[@MunsifMAhmad]

Thanks:)
Soon will upload more videos on Assertions.

[@ajaz4manu]

Pls add more videos on assertions

[@MunsifMAhmad]

Sure, due to time constraints not able to add more videos, but soon will upload more videos on Assertions..
Thanks :)

[@keerthianil680]

Please upload more videos sir!!!

[@MunsifMAhmad]

Soon will upload more videos..